UCC28951
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ZHCSIQ7A –AUGUST 2018 –REVISED DECEMBER 2021
备注
The FETs in this design are driven with a UCC27324 Gate Driver IC, setup to drive 4-A (IP) of gate
drive current.
IP » 4A
(84)
Estimated FET Vds rise and fall time using 方程式85:
100nC - 52nC 48nC
=
tr » tf =
» 24ns
IP
2
4A
2
(85)
Estimate QE and QF FET Losses (PQE) using 方程式86:
P
2
P = IQE_RMS2 ìRds(on)QE
+
ì VdsQE t + t fSW + 2ìCOSS_QE_ AVG ì VdsQE fSW + 2ìQgQE ì VgQEfSW
OUT
(
)
QE
r
f
VOUT
(86)
PQE » 9.3W
(87)
(88)
Recalculate the power budget using 方程式88.
P
= P
- 2´PQE » 6.5W
BUDGET
BUDGET
8.2.2.9 Input Capacitance (CIN)
The input voltage in this design is 390 VDC, which is typically fed by the output of a PFC boost pre-regulator. It is
typical to select input capacitance based on holdup and ripple requirements.
备注
The delay time needed to achieve ZVS can act as a duty cycle clamp (DCLAMP).
Calculate tank frequency using 方程式89:
1
fR =
2p LS ´(2´COSS _ QA _ AVG
)
(89)
(90)
Estimate the delay time using 方程式90:
2
tDELAY
=
» 314ns
f R´4
The effective duty cycle clamp (DCLAMP) is calculated in 方程式91:
≈
∆
«
’
1
DCLAMP
=
- tDELAY ì 2ì f = 94%
÷
SW
2ì fSW
◊
(91)
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English Data Sheet: SLUSDB2
54
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