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TVP5160PNP 参数 Datasheet PDF下载

TVP5160PNP图片预览
型号: TVP5160PNP
PDF下载: 下载PDF文件 查看货源
内容描述: NTSC / PAL / SECAM /组件2×10位数字视频解码器 [NTSC/PAL/SECAM/Component 2x10-Bit Digital Video Decoder]
分类和应用: 解码器
文件页数/大小: 111 页 / 1417 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TVP5160  
SLES135EFEBRUARY 2005REVISED APRIL 2011  
www.ti.com  
Table 3-78. F- and V-Bit Decode Control  
Subaddress 69h  
Default  
00h  
7
6
5
4
3
2
1
0
VPLL  
Adaptive  
Reserved  
F-Mode[1:0]  
This register only works in manual gain control mode. When AGC is active, writing to any value is ignored.  
F-bit control mode  
00 = Auto: If lines per frame is standard decode F and V bits as per 656 standard from line count else decode F bit from vsync input  
and set V bit = 0b  
01 = Decode F and V bits from input syncs  
10 = Reserved  
11 = Always decode F and V bits from line count (TVP5146 compatible)  
This register is used in conjunction with register 75h as indicated below:  
REGISTER 69H  
REGISTER 75H  
STANDARD LPF  
NONSTANDARD LPF  
MODE  
BIT 1  
BIT 0  
BIT 3  
BIT 2  
F
V
F
V
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved  
TVP5160  
TVP5160  
Reserved  
Reserved  
Reserved  
656  
Reserved  
656  
Reserved  
Toggle  
Reserved  
Switch9  
0
656  
656  
Pulse  
Reserved  
Reserved  
656  
Reserved  
Reserved  
656  
Reserved  
Reserved  
Toggle  
Reserved  
Reserved  
Switch9  
0
656  
656  
Pulse  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Even = 1  
Odd = toggle  
1
1
0
0
TVP5146  
656  
656  
Switch  
1
1
1
1
1
1
0
1
1
1
0
1
TVP5146  
TVP5146  
Reserved  
656  
656  
656  
656  
Toggle  
Pulse  
Switch  
Switch  
Reserved  
Reserved  
Reserved  
Reserved  
656 = ITU-R BT.656 standard  
Pulse = Pulses low for 1 line prior to field transition  
Switch = V bit switches high before the F-bit transition and low after the F bit transition  
Switch9 = V bit switches high 1 line prior to the F-bit transition, then low after 9 lines  
Reserved = Not used  
Adaptive  
0 = Enable F- and V-bit adaptation to detected lines per frame  
1 = Disable F- and V-bit adaptation to detected lines per frame  
VPLL time constant control:  
0 = VPLL adapts time constants to input signal  
1 = VPLL time constants fixed  
70  
Internal Control Registers  
Copyright © 20052011, Texas Instruments Incorporated  
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