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TVP5160PNP 参数 Datasheet PDF下载

TVP5160PNP图片预览
型号: TVP5160PNP
PDF下载: 下载PDF文件 查看货源
内容描述: NTSC / PAL / SECAM /组件2×10位数字视频解码器 [NTSC/PAL/SECAM/Component 2x10-Bit Digital Video Decoder]
分类和应用: 解码器
文件页数/大小: 111 页 / 1417 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TVP5160  
www.ti.com  
SLES135EFEBRUARY 2005REVISED APRIL 2011  
Table 3-63. AFE Fine Gain for CVBS/Luma  
Subaddress 50h51h  
Default  
900h  
Subaddress  
50h  
7
6
5
4
3
2
1
0
FGAIN 4 [7:0]  
51h  
Reserved  
FGAIN 4 [11:8]  
FGAIN 4 [11:0]: This fine gain applies to CVBS or S-Video luma (see AFE fine gain for Pb register)  
This register is only updated when the MSB (register 51h) is written to.  
This register only works in manual gain control mode. When AGC is active, writing to any value is ignored.  
1111 1111 1111 = 1.9995  
1100 0000 0000 = 1.5  
1001 0000 0000 = 1.25 (default)  
1000 0000 0000 = 1  
0100 0000 0000 = 0.5  
0011 1111 1111 to 0000 0000 0000 = Reserved  
Table 3-64. 656 Version  
Subaddress 57h  
Default  
00h  
7
6
5
4
3
2
1
0
Reserved  
656 version  
Reserved  
656 version  
0 = Timing confirms to ITU-R BT.656-4 specifications (default)  
1 = Timing confirms to ITU-R BT.656-3 specifications  
Table 3-65. SDRAM Control  
Subaddress 59h  
Default 00h  
7
6
5
4
3
2
1
0
Reserved  
SDRAM_CLK delay control  
Enable  
Configuration[1:0]  
Configuration[1:0]  
Bit 1  
Bit 0  
Arrangement  
0
0
1
1
0
1
0
1
2 banks × 2048 rows × 256 columns  
4 banks × 2048 rows × 256 columns  
2 banks × 4096 rows × 256 columns  
4 banks × 4096 rows × 256 columns  
16 Mbits  
32 Mbits  
32 Mbits  
64 Mbits  
Memories with more rows, columns, and/or banks can be used as long as the minimum requirements are met. Additional rows, columns,  
and/or banks are ignored and unused by the memory controller.  
The memory controller must be configured before enabling 3DYC or 3DNR; otherwise, incorrect operation of the memory controller will  
result.  
Enable:  
0 = SDRAM controller disabled (default)  
1 = SDRAM controller enabled  
SDRAM_CLK delay control[3:0]  
This register changes the delay from the default position of SDRAM_CLK in increments of approximately 0.58 ns.  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Delay  
0 (default)  
0.58 ns  
1.16 ns  
9.3 ns  
0
0
1
1
0
0
0
1
0
0
0
1
0
1
0
1
Copyright © 20052011, Texas Instruments Incorporated  
Internal Control Registers  
67  
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