TVP5160
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SLES135E–FEBRUARY 2005–REVISED APRIL 2011
Table 3-73. "Blue" Screen Cr Control
Subaddress 61h
Default
80h
7
6
5
4
3
2
1
0
Cr value [9:2]
The Cr value of the color screen output when enabled by bit 2 or 3 of the output formatter 2 register is programmable using a 10-bit value.
The 8 MSB, bits[9:2], are represented in this register. The remaining two LSB are found in the "Blue" screen LSB register. The default color
screen output is black.
Table 3-74. "Blue" Screen LSB Control
Subaddress 62h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Y value LSB [1:0]
Cb value LSB [1:0]
Cr value LSB [1:0]
The two LSB for the "Blue" screen Y, Cb, and Cr values are represented in this register.
Table 3-75. Noise Measurement
Subaddress 64h–65h
Read only
Subaddress
64h
7
6
5
4
3
2
1
0
3DNR Noise Measurement [7:0]
3DNR Noise Measurement [15:8]
65h
3DNR Noise Measurement
Because this register is a double-byte register it is necessary to capture the setting into the register to ensure that the value is not updated
between reading the lower and upper bytes. To cause this register to capture the current settings, bit 0 of I2C register 97h (status request)
must be set to 1b. Once the internal processor has updated this register bit 0 of register 97h is cleared, indicating that both bytes of the
noise measurement register have been updated and can be read. Either byte may be read first, because no further update will occur until
bit 0 of 97h is set to 1b again.
Table 3-76. 3DNR Y Core0
Subaddress 66h
Read only
7
6
5
4
3
2
1
0
Y_core0[7:0]
Y Core0
Table 3-77. 3DNR UV Core0
Subaddress 67h
Read only
7
6
5
4
3
2
1
0
UV_core0[7:0]
UV Core0
Copyright © 2005–2011, Texas Instruments Incorporated
Internal Control Registers
69
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