TUSB1310A
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SLLSE32D–NOVEMBER 2010–REVISED MAY 2011
3.4 Receiver Status
The TUSB1310A has an elastic buffer for clock tolerance compensation, the Link Partner detection, and
some received data error detections. The receive data status from SSRXP/SSRXN differential pair
presents on RX_STATUS2-0. If an error occurs during a SKP ordered-set, the error signaling has
precedence. If more than one error occurs on a received byte, the errors have the priority below.
1. 8B/10B decode error
2. Elastic buffer overflow
3. Elastic buffer underflow (Can not occur in Nominal Empty buffer model)
4. Disparity error
3.4.1 Clock Tolerance Compensation
The receiver contains an elastic buffer used to compensate for differences in frequencies between bit
rates at the two ends of a Link. The elastic buffer must be capable of holding enough symbols to handle
worst case differences in frequency and worst case intervals between SKP ordered-sets. A SKP order-set
is a set of symbols transmitted as a group. The SKP ordered-sets allows the receiver to adjust the data
stream being received prevent the elastic buffer from either overflowing or under-flowing due to any clock
tolerance differences.
The TUSB1310A supports two models, Nominal Half Full buffer model and Nominal Empty buffer mode.
For the Nominal Half Full buffer model, the TUSB1310A monitors the receive data stream. When a Skip
ordered-set is received, the TUSB1310A adds or removes one SKP order set from each SKP to manage
its elastic buffer to keep the buffer as close to half full as possible. Only full SKP ordered sets are added
or removed. When a SKP order set is added, the TUSB1310A asserts an “Add SKP” code (001b) on the
RX_STATUS for one clock cycle. When a SKP order set is removed, the RX_STATUS is has a “Remove
SHP” code (010b).
For the Nominal Empty buffer model the TUSB1310A attempts to keep the elasticity buffer as close to
empty as possible. When no SKP ordered sets have been received, the TUSB1310A will be required to
insert SKP ordered sets into the received data stream.
Table 3-4. RX_STATUS - SKP
RX_STATUS2-0
001b
SKP ADDITION OR REMOVAL
1 SKP Ordered Set added
LENGTH
One clock cycle
010b
1 SKP Ordered Set removed
3.4.2 Receiver Detection
TX_DETRX_LPBK starts a receiver detection operation to determine if there is a receiver at the other end
of the link. When the receiver detect sequence completes, the PHY_STATUS is asserted for one clock
and drives the RX_STATUS signals to the appropriate code. Once the TX_DETRX_LPBK signal is
asserted, the Link Layer Controller must leave the signal asserted until the PHY_STATUS pulse. When
receiver detection is performed in P3, the PHY_STATUS shows the appropriate receiver detect value until
the TX_DETRX_LPBK is de-asserted.
Table 3-5. RX_STATUS - Receiver Detection
RX_STATUS2-0
000b
DETECTED CONDITION
Receiver not present
Receiver present
LENGTH
One clock cycle
011b
Copyright © 2010–2011, Texas Instruments Incorporated
FUNCTIONAL DESCRIPTION
21
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