TUSB1310A
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SLLSE32D–NOVEMBER 2010–REVISED MAY 2011
4.2.2 Function Control (04h-06h)
Address: 04h-06h (Read), 04h (Write), 05h (Set), 06h (Clear)
Table 4-4. Function Control
BITS
NAME
ACCESS
RESET
DESCRIPTION
Selects the required transceiver speed 00b : Enable HS
transceiver
01b: Enable FS transceiver
10b: Enable LS transceiver
1:0
XcvrSelect
Rd/Wr/S/C
1h
11b: Enable FS transceiver for LS packets
(FS preamble is automatically pre-pended)
Controls the internal 1.5-kΩ pullup resister and 45-Ω HS
terminations. Control over bus resistors changes depending
on XcvrSelect, OpMode, DpPulldown and DmPulldown. Since
low speed peripherals never support full speed or hi-speed,
providing the 1.5 kΩ on DM for low speed is optional.
2
TermSelect
OpMode
Rd/Wr/S/C
Rd/Wr/S/C
0
Selects the required bit encoding style during transmit
00 : Normal operation
01: Non-driving
10: Disable bit-stuff and NRZI encoding
11: Do not automatically add SYNC and EOP when
transmitting. Must be used only for HS packets.
4:3
00
Active High transceiver reset. After the Link sets this bit, the
TUSB1310A must assert the ULPI_DIR and reset the ULPI.
When the reset is completed, the PHY de-asserts the
ULPI_DIR and automatically clears this bit. After de-asserting
the ULPI_DIR, the PHY must re-assert the ULPI_DIR and
send an RX CMD update on the Link Layer Controller. The
Link Layer Controller must wait for the ULPI_DIR to de-
assert before using the ULPI bus. Does not reset the ULPI or
ULPI register set.
5
Reset
Rd/Wr/S/C
0
Active low PHY suspend. Put the TUSB1310A into Low
Power Mode. The PHY can power down all blocks except the
full speed receiver, OTG com-parators, and the ULPI pins.
The PHY must auto-matically set this bit to 1 when Low
Power Mode is exited.
6
7
SuspendM
Reserved
Rd/Wr/S/C
Rd
1h
0
0: Low Power Mode
1: Powered
Reserved
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