TRF6900
SINGLE-CHIP RF TRANSCEIVER
SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000
TRF6900 direct digital synthesizer implementation (continued)
Channel width (frequency deviation) for 2-FSK modulation and channel spacing are software programmable.
The minimum channel width and minimum channel spacing depend on the RF system frequency plan.
Since the DDS registers are static, preprogrammed values are retained during standby mode. This feature
greatly reduces turn on time, reduces current consumption when coming out of standby mode, and enables very
fast lock-times. The PLL lock-times ultimately determine when data can be transmitted or received.
phase-locked loop
The phase-locked loop (PLL) of the TRF6900 consists of a phase detector (PD) and a frequency acquisiton aid
(FD), two charge pumps, an external loop filter, a voltage controlled oscillator (VCO), and a programmable fixed
prescaler (N-divider) in the feedback loop (see Figure 18).
The PLL as implemented in the TRF6900 multiplies the DDS output frequency and further suppresses the
unwanted spurious signals produced by the direct digital synthesizer.
10
PD
ƒ
I
I
DDS
PD_1
DDS
ƒ
out
13, 14
External
Loop Filter
VCO
PD_2
9
FD
ƒ
ref
N-Divider
256 / 512
Figure 18. Basic PLL Structure
VCO
A modified Colpitts oscillator architecture with an external resonant circuit is used for the TRF6900. The internal
bias current network adjusts the signal amplitude of the VCO. This allows a wide range of Q-factors (30….60)
for the external tank circuit.
The VCO can be bypassed by applying an external RF signal at VCO_TANK2, terminal 14. To drive the internal
PLL and power amplifier, a typical level of –10 dBm should be applied. When an external VCO is used, the
x_VCO bit should be set to 0.
phase detector and charge pumps
The TRF6900 contains two charge pumps for locking to the desired frequency; one for coarse tuning of the
frequency differences (called the frequency acquisition aid), and one for fine tuning of the phase differences
(used in conjunction with the phase detector).
The XOR phase detector and charge pumps produce a mean output current that is proportional to the phase
difference between the reference frequency and the VCO frequency divided by N; N=256 or 512. The TRF6900
generates the current pulses I
during normal operation (PLL locked).
PD_1
An additional slip detector and acquisition aid charge pump generates current pulses at terminal PD_OUT2
during the lock-in of the PLL. This charge pump is turned off when the PLL locks in order to reduce current
consumption. The multiplication factor of the acquisition aid current I
(APLL) in the C-word.
can be programmed by three bits
PD_2
The slip detector output, PD_OUT2, at terminal 9 should be connected directly to the loop filter capacitor C ,
1
as in Figure 21. The nominal charge pump current I is determined by the external resistor R , connected to
0
PD
terminal 8, and can be calculated as follows:
7 V
R
PD
I
0
19
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