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TRF6900PTR 参数 Datasheet PDF下载

TRF6900PTR图片预览
型号: TRF6900PTR
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用: 电信集成电路蜂窝电话电路电信电路射频
文件页数/大小: 34 页 / 485 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TRF6900  
SINGLE-CHIP RF TRANSCEIVER  
SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000  
direct digital synthesizer  
general principles of DDS operation  
In general, a direct digital synthesizer (DDS) is based on the principle of generating a sinewave signal in  
the digital domain. Benefits include high precision, wide frequency range, a high degree of software  
programmability, and extremely fast lock times.  
AblockdiagramofatypicalDDSisshowninFigure15. Itgenerallyconsistsofanaccumulator, sinelookuptable,  
a digital-to-analog converter, and a low-pass filter. All digital blocks are clocked by the reference oscillator.  
Synthesizer  
Sine  
Lookup  
Table  
Low-Pass  
Filter  
Analog Output Signal  
+
DAC  
N-Bit Register  
Frequency Register  
Load With Frequency Word  
Figure 15. Typical DDS Block Diagram  
N
The DDS constructs an analog sine waveform using an N-bit adder counting up from 0 to 2 in steps of the  
frequency register, whereby generating a digital ramp waveform. Each number in the N-bit output register is  
used to select the corresponding sine wave value out of the sine lookup table. After the digital-to-analog  
conversion, a low-pass filter is necessary to suppress unwanted spurious responses.  
The analog output signal can be used as a reference input signal for a phase locked loop. The PLL circuit then  
multiplies the reference frequency by a predefined factor.  
TRF6900 direct digital synthesizer implementation  
A block diagram of the DDS implemented in the TRF6900 is shown in Figure 16. It consists of a 24-bit  
accumulator clocked by the reference oscillator along with control logic settings.  
24  
ƒ
to  
PLL  
DDS  
11-Bit  
DAC  
Sine  
Shaper  
Low-pass  
Filter  
+
Reference Frequency, ƒ  
24-Bit  
Register  
ref  
11  
DDS Frequency Register  
24  
MODE – (Terminal 17)  
22  
22  
DDS Mode0  
A – Word  
B – Word  
Frequency Setting  
Mode0/1  
Modulation  
Control  
Logic  
Select  
Logic  
+
TX_DATA – (Terminal 19)  
DDS Mode1  
Frequency Setting  
D – Word / DEV Bits  
(FSK Deviation)  
FSK Frequency  
Deviation Register  
C – Word / MM Bit  
8
(Modulation Mode Select)  
Figure 16. DDS Block Diagram as Implemented in the TRF6900  
17  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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