TRF6900
SINGLE-CHIP RF TRANSCEIVER
SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000
data slicer (continued)
The integrator, acting as an error amplifier, takes the low-pass filtered output signal and generates a control
voltage proportional to the frequency error of the external tank circuit as compared to the limiter output signal.
By adjusting the value of the internal variable inductor, this control voltage is used to fine-tune the external tank
to its nominal value.
The acquisition time of the AFC loop can be adjusted by an external capacitor connected to terminal 29,
S&H_CAP. This capacitor determines the integration time constant of the integrator while in learning mode. As
a rule of thumb, the time constant of the AFC loop should be at least five times greater than the baseband signal
fundamental period.
The time constant of the entire AFC control loop can be calculated as follows:
22 k
C
terminal 29
AFC
The automatic frequency control loop controls the resonant frequency of the external LC tank without any
additional external adjustments as long as learning mode operation is selected. If hold mode is selected, the
AFC loop is open and an external dc voltage can be applied at terminal 29 to set the threshold of the data slicer.
During learning mode, a precharged capacitor (connected to terminal 29, S&H_CAP) can be used to set the
dc threshold voltage of the data slicer in hold mode.
In other words, the data slicer constantly integrates the incoming signal during the learning sequence
(0,1,0,1. . .) and charges the external capacitor connected to terminal 29, S&H_CAP to a dc voltage level, V
,
ref
that is proportional to the average demodulation dc level. After a predefined time (dependent upon the
application), the data slicer is switched to hold mode. The data slicer stops integrating and uses the voltage
stored on the external capacitor as the decision threshold between a logic 0 or a logic 1 on the DATA_OUT
terminal 28.
reference oscillator
The reference oscillator provides the DDS system clock. It allows operation, with a suitable external crystal,
between 15 MHz and 26 MHz.
An external oscillator may be used to supply clock frequencies between 15 MHz and 26 MHz. The external
oscillator should be directly connected to XOSC2, terminal 24. The other oscillator terminal (XOSC1, terminal
23) should be left open or can be used as a buffered version of the signal applied at terminal 24 (see Figure 14).
The same crystal or externally supplied oscillator signal is used to derive both the transmit and receive
frequencies.
XOSC1
XOSC2
23
24
NC
External Signal, ƒ
ref
Figure 14. Applying an External Oscillator Signal
16
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