TRF6900
SINGLE-CHIP RF TRANSCEIVER
SLAS213C – SEPTEMBER 1999 – REVISED MAY 2000
TRF6900 direct digital synthesizer implementation (continued)
The frequency of the reference oscillator, ƒ , is the DDS sample frequency, which also determines the
ref
maximum DDS output frequency. Together with the accumulator width (in bits), the frequency resolution of the
DDS can be calculated. Multiplied by the divider ratio (prescaler) of the PLL, N, the minimum frequency step
size of the TRF6900 is calculated as follows:
ƒ
ref
24
ƒ
N
2
The 24-bit accumulator can be programmed via two 22-bit frequency setting registers (the A-word determines
the mode0 frequency, the B-word determines the mode1 frequency) with the two MSB bits set to zero.
Consequently, the maximum bit weight of the DDS system is reduced to 1/8 (see Figure 17). This bit weight
corresponds to a VCO output frequency of (ƒ /8) × N. Depending on the MODE terminal’s (terminal 17) logic
ref
level, the internal mode select logic loads the frequency register with either the DDS_0 or DDS_1 frequency
(see Figure 16 and Figure 17).
22
DDS Frequency Setting For Mode0/1
From A-Word/B-Word
DDS Frequency Register
X X X X X
LSB
0
0 X X . . . .
. . .
. . .
MSB
23 22 21 20 . . .
4
3
2
1
0
Bit weight:
1/2 1/4 1/8 1/16 . . .
. . .
1
24
2
8
FSK Frequency Deviation Register – DEV
. . . .
. . . .
. . . .
. . . .
0
0
X X X X X X X X 0
0
DDS Frequency Register
MSB
23 22
LSB
1 0
9
8
7
6
5
4
3
2
Figure 17. Implementation of the DDS Frequency and FSK Frequency
Deviation in the DDS Frequency Register
The VCO output frequency, ƒ , which is dependent on the DDS_x frequency settings ( DDS_0 in the A-word
out
or DDS_1 in the B-word ), can be calculated as follows:
ƒ
ƒ
DDS_x
24
ref
24
ref
ƒ
DDS_x
N
N
out
2
2
If FSK modulation is selected (MM=0; C-Word, bit 16) the 8-bit FSK deviation register can be used to program
the frequency deviation of the 2-FSK modulation. Figure 17 illustrates where the 8 bits of the FSK deviation
register map into the 24-bit DDS frequency register. Since the two LSBs are set to zero, the total FSK deviation
can be determined as follows:
DEV
ƒ
ref
ƒ
N
2–FSK
22
2
Hence, the 2-FSK frequency, set by the level of TX_DATA, is calculated as follows:
(
)
DEV
ƒ
DDS_x
24
ƒ
DDS_x
4
ref
ref
ƒ
N
ƒ
N
out1:TX_DATA Low
out2:TX_DATA High
24
2
2
This frequency modulated output signal is used as a reference input signal for the PLL circuit.
18
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