TPS65910, TPS65910A, TPS65910A3, TPS659101, TPS659102, TPS659103
TPS659104, TPS659105, TPS659106, TPS659107, TPS659108, TPS659109
www.ti.com
SWCS046N –MARCH 2010–REVISED APRIL 2012
•
Or interrupt flag active (default INT1 low) while the device is off (NRESPWRON = 0) generates a power-
on enable condition during a fixed delay (TDOINT1 pulse duration defined in POWER CONTROL TIMING,
Power Control Timing).
The power-on enable condition pulse occurs only if the interrupt status bit is initially low (no previous
identical interrupt pending in the status register).
The Interrupt sources expected when the device is off are:
•
•
PWRON low-level interrupt (PWRON_IT = 1 in INT_STS_REG register)
PWRHOLD rising-edge interrupt (PWRHOLD_IT = 1 in INT_STS_REG register)
The Interrupt sources expected if enabled when the device is off are:
•
•
RTC Alarm interrupt (RTC_ALARM_IT = 1 or RTC_PERIOD_IT = 1 in INT_STS_REG register)
First-time input voltage rising above VMBHI threshold (Boot mode or EEPROM dependent) and input
voltage > VMBCH threshold (VMBCH_IT = 1 in INT_STS_REG register).
GPIO_CKSYNC cannot be used to turn on the device (OFF-to-ACTIVE state transition), even if its associated
interrupt is not masked, but can be used as an interrupt source to wake up the device from SLEEP-to-ACTIVE
state.
Device power-on disable conditions:
•
PWRON signal low level during more than the long-press delay: tdPWRONLP (can be disabled though register
programming). The interrupt corresponding to this condtion is PWRON_LP_IT in the INT_STS_REG register.
•
•
Or Die temperature has reached the thermal shutdown threshold.
Or DEV_OFF or DEV_OFF_RST control bit set to 1 (value of DEV_OFF is cleared when the device is in OFF
state).
Device SLEEP enable conditions:
•
•
•
SLEEP signal low level (default, or high level depending on the programmed polarity)
And DEV_SLP control bit set to 1
And interrupt flag inactive (default INT1 high): no nonmasked interrupt pending
The SLEEP state can be controlled by programming DEV_SLP and keeping the SLEEP signal in the active
polarity state, or it can be controlled through the SLEEP signal setting the DEV_SLP bit to 1 once, after device
turn-on.
SWITCH-ON/-OFF SEQUENCES
The power sequence is the automated switching on of the device resources when an off-to-active transition takes
place.
The device supports three embedded power sequences selectable by the device BOOT pins.
BOOT0
BOOT1
Processor Supported
0
1
0
0
0
1
AM3517, AM3505
OMAP3 Family, AM3715/03, DM3730/25
EEPROM sequence
Details of the boot sequence timing are given in SWITCH-ON/-OFF SEQUENCES AND TIMING. EEPROM
sequences can be used for specific power up sequence for corresponding application processor. For details of
EEPROM
sequence
refer
to
the
user
guides
on
the
product
folder:
http://focus.ti.com/docs/prod/folders/print/tps65910.html.
CONTROL SIGNALS
SLEEP
When none of the device sleep-disable conditions are met, a falling edge (default, or rising edge, depending on
the programmed polarity) of this signal causes an ACTIVE-to-SLEEP state transition of the device. A rising edge
(default, or falling edge, depending on the programmed polarity) causes a transition back to ACTIVE state. This
input signal is level sensitive and no debouncing is applied.
Copyright © 2010–2012, Texas Instruments Incorporated
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Product Folder Link(s): TPS65910 TPS65910A TPS65910A3 TPS659101 TPS659102 TPS659103 TPS659104
TPS659105 TPS659106 TPS659107 TPS659108 TPS659109
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