TPS61196
SLVSBG1C –OCTOBER 2012–REVISED FEBRUARY 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
TA
PACKAGE
ORDERING PART NUMBER
TOP MARK
-40°C to 85°C
28-Pin HTSSOP
TPS61196PWPR
TPS61196
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
UNIT
MAX
33
Pin VIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–2.0
–0.3
Pin FAULT
Pin IFB1 to IFB6
VIN
40
Pin FBP, ISET, ISNS, IFBV
Voltage range(2)
3.3
20
V
Pin EN, PWM1 to PWM6
Pin GDRV
7.0
9.0
7.0
2
Pin GDRV 10ns transient
All other pins
HBM
kV
V
ESD rating
MM
200
1
CDM
kV
Continuous power dissipation
Operating junction temperature range
Storage temperature range
See Thermal Information Table
–40
–65
150
150
°C
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal
THERMAL INFORMATION
TPS61196
THERMAL METRIC(1)
UNITS
PWP (28 PINS)
θJA
Junction-to-ambient thermal resistance
33.8
18.8
15.6
0.6
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
15.4
2.5
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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