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SLVS398D − JUNE 2001 − REVISED JULY 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
A
OUTPUT VOLTAGE
PACKAGE
PART NUMBER
(1)
−40°C to 85°C
Adjustable down to 0.9 V
Plastic HTSSOP (PWP)
TPS54610PWP
(1)
The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54610PWPR). See the application section of
the data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TPS54610
−0.3 V to 7 V
−0.3 V to 6 V
−0.3 V to 4V
−0.3 V to 17 V
−0.3 V to 7 V
−0.6 V to 10 V
UNIT
VIN, SS/ENA, SYNC
RT
Input voltage range, V
V
I
VSENSE
BOOT
VBIAS, COMP, PWRGD
Output voltage range, V
V
O
PH
PH
Internally Limited
Source current, I
O
COMP, VBIAS
PH
6
mA
A
12
6
COMP
Sink current, I
S
mA
SS/ENA, PWRGD
AGND to PGND
10
Voltage differential
Operating virtual junction temperature range, T
0.3
V
−40 to 125
−65 to 150
300
°C
°C
°C
J
Storage temperature, T
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Input voltage, V
3
6
V
I
Operating junction temperature, T
−40
125
°C
J
DISSIPATION RATINGS(1)(2)
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
T
= 25°C
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING POWER RATING POWER RATING
(3)
28 Pin PWP with solder
18.2 °C/W
40.5 °C/W
5.49 W
3.02 W
1.36 W
2.20 W
0.99 W
28 Pin PWP without solder
2.48 W
(1)
(2)
For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
Test board conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
Maximum power dissipation may be limited by over current protection.
(3)
2
TI [ TEXAS INSTRUMENTS ]
