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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
PIN ASSIGNMENTS
PWP PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
VIN
VIN
UVLO
PWRGD
RT
SYNC
ENA
COMP
BOOT
PH
PH
15
14
13
12
11
10
9
LSG
THERMAL
PAD
VBIAS
PGND
AGND
VSENSE
NOTE:
If there is not a Pin 1 indicator, turn device to enable
readingthe symbol from left to right. Pin 1 is at the lower
left corner of the device.
Terminal Functions
TERMINAL
DESCRIPTION
NO.
1, 2
3
NAME
VIN
Input supply voltage, 4.5 V to 20 V. Must bypass with a low ESR 10-µF ceramic capacitor.
UVLO
PWRGD
RT
Undervoltage lockout pin. Connecting an external resistive voltage divider from VIN to the pin will override the internal
default VIN start and stop thresholds.
4
5
6
Power good output. Open drain output. A low on the pin indicates that the output is less than the desired output voltage.
There is an internal rising edge filter on the output of the PWRGD comparator.
Frequency setting pin. Connect a resistor from RT to AGND to set the switching frequency. Connecting the RT pin to
ground or floating will set the frequency to an internally preselected frequency.
SYNC
Bidirectionalsynchronization I/O pin. SYNC pin is an output when the RT pin is floating or connected low. The output is a
fallingedge signal out of phase with the rising edge of PH. SYNC may be used as an input to synchronize to a system clock
by connecting to a falling edge signal when an RT resistor is used. See 180° Out of Phase Synchronization operation in the
ApplicationInformation section.
7
8
ENA
Enable. Below 0.5 V, the device stops switching. Float pin to enable.
COMP
VSENSE
AGND
PGND
Error amplifier output. Connect frequency compensation network from COMP to VSENSE pins.
Inverting node error amplifier.
9
10
11
Analog ground—internally connected to the sensitive analog ground circuitry. Connect to PGND and PowerPAD.
Power Ground—Noisy internal ground—Return currents from the LSG driver output return through the PGND pin. Con-
nect to AGND and PowerPAD.
12
13
VBIAS
LSG
Internal 8.0V bias voltage. A 1.0 uF ceramic bypass capacitance is required on the VBIAS pin.
Gate drive for optional low side MOSFET. Connect gate of n-channel MOSFET for a higher efficiency synchronous buck
converter configuration. Otherwise, leave open and connect schottky diode from ground to PH pins.
14, 15 PH
16 BOOT
Phase node—Connect to external L−C filter.
Bootstrap capacitor for high side gate driver. Connect 0.1 µF ceramic capacitor from BOOT to PH pins.
PowerPAD PGND and AGND pins must be connected to the exposed pad for proper operation. See Figure 21 for an example PCB
layout.
5
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