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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
bandgap and scaling circuits are trimmed to produce
0.891 V at the output of the error amplifier, with the
amplifier connected as a voltage follower. The trim
procedure improves the regulation, since it cancels offset
errors in the scaling and error amplifier circuits.
Power Good (PWRGD)
The VSENSE pin is compared to an internal reference
signal, if the VSENSE is greater than 97% and no other
faults are present, the PWRGD pin presents a high
impedance. A low on the PWRGD pin indicates a fault. The
PWRGD pin has been designed to provide a weak
pull−down and indicates a fault even when the device is
unpowered. If the TPS54350 has power and has any fault
flag set, the TPS54350 indicates the power is not good by
driving the PWRGD pin low. The following events, singly
or in combination, indicate power is not good:
PWM Control and Feed Forward
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, PWM latch, and the
adaptive dead-time control logic. During steady-state
operation below the current limit threshold, the PWM
comparator output and oscillator pulse train alternately
reset and set the PWM latch.
D
D
D
D
D
D
D
VSENSE pin out of bounds
Overcurrent
Thermal shutdown
UVLO undervoltage
Input voltage not present (weak pull-down)
Slow-starting
Once the PWM latch is reset, the low-side driver and
integrated pull-down MOSFET remain on for a minimum
duration set by the oscillator pulse width. During this
period, the PWM ramp discharges rapidly to the valley
voltage. When the ramp begins to charge back up, the
low-side driver turns off and the high-side FET turns on.
The peak PWM ramp voltage varies inversely with input
voltage to maintain a constant modulator and power stage
gain of 8 V/V.
VBIAS voltage is low
Once the PWRGD pin presents a high impedance (i.e.,
power is good), a VSENSE pin out of bounds condition
forces PWRGD pin low (i.e., power is bad) after a time
delay. This time delay is a function of the switching
frequency and is calculated using equation 5:
1000
T
+
ms
As the PWM ramp voltage exceeds the error amplifier
output voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side driver remains on until the next
oscillator pulse discharges the PWM ramp.
delay
ƒ
s(kHz)
(5)
Bias Voltage (VBIAS)
The VBIAS regulator provides a stable supply for the
internal analog circuits and the low side gate driver. Up to
1 mA of current can be drawn for use in an external
application circuit. The VBIAS pin must have a bypass
capacitor value of 1.0 µF. X7R or X5R grade dielectric
ceramic capacitors are recommended because of their
stable characteristics over temperature.
During transient conditions, the error amplifier output can
be below the PWM ramp valley voltage or above the PWM
peak voltage. If the error amplifier is high, the PWM latch
is never reset and the high-side FET remains on until the
oscillator pulse signals the control logic to turn the
high-side FET off and the internal low-side FET and driver
on. The device operates at its maximum duty cycle until the
output voltage rises to the regulation set point, setting
VSENSE to approximately the same voltage as the
internal voltage reference. If the error amplifier output is
low, the PWM latch is continually reset and the high-side
FET does not turn on. The internal low-side FET and low
side driver remain on until the VSENSE voltage decreases
to a range that allows the PWM comparator to change
states. The TPS54350 is capable of sinking current
through the external low side FET until the output voltage
reaches the regulation set point.
Bootstrap Voltage (BOOT)
The BOOT capacitor obtains its charge cycle by cycle from
the VBIAS capacitor. A capacitor from the BOOT pin to the
PH pins is required for operation. The bootstrap
connection for the high side driver must have a bypass
capacitor of 0.1 µF.
Error Amplifier
The VSENSE pin is the error amplifier inverting input. The
error amplifier is a true voltage amplifier with 1.5 mA of
drive capability with a minimum of 60 dB of open loop
voltage gain and a unity gain bandwidth of 2 MHz.
The minimum on time is designed to be 180 ns. During the
internal slow-start interval, the internal reference ramps
from 0 V to 0.891 V. During the initial slow-start interval, the
internal reference voltage is very small resulting in a
couple of skipped pulses because the minimum on time
causes the actual output voltage to be slightly greater than
the preset output voltage until the internal reference ramps
up.
Voltage Reference
The voltage reference system produces a precision
reference signal by scaling the output of a temperature
stable bandgap circuit. During production testing, the
9
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