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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
This pole is used to set the overall gain of the compensated
error amplifier and determines the closed loop crossover
frequency. Since R1 is given as 1 kΩ and the crossover
BIAS AND BOOTSTRAP CAPACITORS
Every TPS54350 design requires a bootstrap capacitor,
C3 and a bias capacitor, C4. The bootstrap capacitor must
be 0.1 µF. The bootstrap capacitor is located between the
PH pins and BOOT pin. The bias capacitor is connected
between the VBIAS pin and AGND. The value should be
1.0 µF. Both capacitors should be high quality ceramic
types with X7R or X5R grade dielectric for temperature
stability. They should be placed as close to the device
connection pins as possible.
frequency is selected as 30 kHz, the desired f
calculated with equation 24:
can be
INT
–0.9
10
ƒ
CO
ƒ
+
INT
2
(25)
And the value for C6 is given by equation 25:
1
LOW-SIDE FET
C6 +
2pR1ƒ
INT
(26)
The TPS54350 is designed to operate using an external
low-side FET, and the LSG pin provides the gate drive
output. Connect the drain to the PH pin, the source to
PGND, and the gate to LSG. The TPS54350 gate drive
circuitry is designed to accommodate most common
n-channel FETs that are suitable for this application. The
SWIFT Designer Software can be used to calculate all the
design parameters for low-side FET selection. There are
some simplified guidelines that can be applied that
produce an acceptable solution in most designs.
The first zero, f , is located at one half the output filter LC
corner frequency, so R3 can be calculated from:
Z1
1
R3 +
pC6ƒ
LC
(27)
The second zero, f , is located at the output filter LC
Z2
corner frequency, so C8 can be calculated from:
1
The selected FET must meet the absolute maximum
ratings for the application:
C8 +
2pR1ƒ
LC
(28)
Drain-source voltage (V ) must be higher than the
DS
The first pole, fP1, is located to coincide with the output
filter ESR zero frequency. This frequency is given by:
maximum voltage at the PH pin, which is V
+ 0.5 V.
INMAX
Gate-source voltage (V ) must be greater than 8 V.
GS
1
ƒ
+
ESR
Drain current ( ) must be greater than 1.1 x I
.
2pR
C
ID
OUTMAX
ESR OUT
(29)
Drain-source on resistance (r
) should be as small as
DSON
where R
output capacitor.
is the equivalent series resistance of the
ESR
possible, less than 30 mΩ is desirable. Lower values for
result in designs with higher efficiencies. It is
r
DSON
important to note that the low-side FET on time is typically
longer than the high-side FET on time, so attention paid to
In this case, the ESR zero frequency is 35.4 kHz, and R5
can be calculated from:
low-side FET parameters can make
improvement in overall efficiency.
a
marked
1
R5 +
2pC8 ƒ
Total gate charge (Q ) must be less than 50 nC. Again,
g
ESR
(30)
lower Q characteristics result in higher efficiencies.
g
The final pole is placed at a frequency above the closed
loop crossover frequency high enough to not cause the
phase to decrease too much at the crossover frequency
while still providing enough attenuation so that there is little
Additionally, check that the device chosen is capable of
dissipating the power losses.
For this design, a Fairchild FDR6674A 30-V n-channel
MOSFET is used as the low-side FET. This particular FET
is specifically designed to be used as a low-side
synchronous rectifier.
or no gain at the switching frequency. The f pole location
P2
for this circuit is set to 4 times the closed loop crossover
frequency and the last compensation component value C7
can be derived as follows:
POWER GOOD
1
The TPS54350 is provided with a power good output pin
PWRGD. This output is an open drain output and is
intended to be pulled up to a 3.3-V or 5-V logic supply. A
10-kΩ, pull-up resistor works well in this application. The
absolute maximum voltage is 6 V, so care must be taken
not to connect this pull-up resistor to VIN if the maximum
input voltage exceeds 6 V.
C7 +
8pR3ƒ
CO
(31)
Note that capacitors are only available in a limited range
of standard values, so the nearest standard value has
been chosen for each capacitor. The measured closed
loop response for this design is shown in Figure 5.
18
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