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www.ti.com
SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
j0.0130
Minimum recommended thermal vias: 4 x
.013 dia. inside powerpad area and
8 PL
Minimum recommended exposed copper
area for powerpad. 5mm stencils may
4 x .013 dia. under device as shown.
Additional .018 dia. vias may be used if top
side Analog Ground area is extended.
require 10 percent larger area.
0.0150
0.06
0.0371
0.0400
0.1970
0.1942
0.0570
0.0400
0.0400
0.0256
Connect Pin 10 AGND
and Pin 11 PGND to
Analog Ground plane in
this area for optimum
performance.
0.1700
0.1340
Minimum recommended top
side Analog Ground area.
0.0690
0.0400
Figure 22. Thermal Considerations for PowerPAD Layout
MODEL FOR LOOP RESPONSE
The Figure 23 shows an equivalent model for the
TPS54350 control loop which can be modeled in a circuit
simulation program to check frequency response and
dynamic load response. The error amplifier in the
TPS54350 is a voltage amplifier with 80 dB (10000 V/V) of
open loop gain. The error amplifier can be modeled using
an ideal voltage-controlled current source as shown in
Figure 23 with a resistor and capacitor on the output. The
TPS54350 device has an integrated feed forward
compensation circuit which eliminates the impact of the
input voltage changes to the overall loop transfer function.
The feed forward gain is modeled as an ideal voltage-
controlled voltage source with a gain of 8 V/V. The 1-mV
ac voltage between nodes a and b effectively breaks the
control loop for the frequency response measurements.
Plotting b/c shows the small-signal response of the power
stage. Plotting c/a shows the small-signal response of the
frequency compensation. Plotting a/b shows the small-
signal response of the overall loop. The dynamic load
response can be checked by replacing the R with a
L
current source with the appropriate load step amplitude
and step rate in a time domain analysis.
L
O
R
dc
a
PH
1 mV
ESR
R
R
L
(switch)
b
C
O
100 mΩ
+
+
–
R5
R1
10 MΩ
TPS54350
8 V/V
–
C8
VSENSE
–
R2
10 MΩ
+
–
+
–
0.891
REF
+
R3
C6
10 MΩ
50 pF
50 µA/V
20 V/V
C7
COMP
c
Figure 23. Model of Control Loop
14