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SLVS456C − OCTOBER 2003 − REVISED OCTOBER 2004
U1
TPS54350PWP
L1
C3
0.1 µF
10 µH
VOUT 3.3 V @ 3 A
6 V − 18 V
+
1
2
1
2
3
16
15
14
13
12
11
10
VIN
BOOT
1
2 3 6 7
PH
VIN
C9
10 µF
C1
Q1
UVLO
PH
LSG
47 µF
R10
Power Good 3.3 V 4
4
PWRGD
RT
4.7 Ω
+
5
6
7
8
C2
VBIAS
100 µF
SYNC
ENA
PGND
AGND
8
5
C4
1 µF
C10
3300 pF
9
COMP
VSENSE
PWRPAD
17
C6
82 nF
R3
768 Ω
Pull up to 3.3 V or 5 V
R1
1 kΩ
C7
1800 pF
R5
137 Ω
C8
33 nF
R2
374 Ω
R4
10 kΩ
Power Good 1.8 V
U2
TPS54350PWP
L2
C5
0.1 µF
10 µH
VOUT 1.8 V @ 3 A
1
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
VIN
BOOT
1
2 3 6 7
PH
VIN
C18
47 µF
C15
10 µF
Q2
UVLO
PH
LSG
R9
4
PWRGD
RT
4.7 Ω
+
C11
100 µF
VBIAS
SYNC
ENA
PGND
AGND
8
5
R13
110 kΩ
C16
1 µF
C14
3300 pF
9
COMP
VSENSE
PWRPAD
17
C13
82 nF
R6
768 Ω
Easy 1805 Out of Phase
Synchronization
R12
1 kΩ
C17
1800 pF
R11
137 Ω
C12
33 nF
Q1, Q2: Fairchild Semiconductor FDR6674A
L1, L2: Vishay IHLP-5050CE
R7
976 Ω
C2, C11: Sanyo 6TPC100M
Figure 26. 3.3-V/1.8-V Power Supply With Sequencing
Figure 26 is an example of power supply sequencing using
two TPS54350s. U1 is used to generate an output of 3.3
V, while the voltage output of U2 is set at 1.8 V, typical I/O
and core voltages for microprocessors and FPGAs. In the
circuit, the 3.3−V supply is designed to power up first. The
PWRGD pin of U1 is tied to the ENA pin of U2 so that the
1.8-V supply starts to ramp up after the 3.3-V supply is
within regulation. Since the RT pin of U1 is floating, the
SYNC pin is an output. This synchronization signal is fed
to the SYNC pin of U2. The RT pin of U2 has a 110-kΩ
resistor to ground, and the SYNC pin for this device acts
as an input. The 1.8-V supply operates synchronously with
the 3.3-V supply and their switching node rising edges are
approximately 180° out of phase allowing for a reduction
in the input voltage ripple. See Figure 19 for this wave
form.
20
TI [ TEXAS INSTRUMENTS ]
