TPS23750
TPS23770
www.ti.com
SLVS590A–JULY 2005–REVISED AUGUST 2005
Buck Converter Example
Figure 40 illustrates a particular form of buck converter where the output is derived with respect to the positive
input rail. The application circuits are connected across the output, shown on J4, with terminal 2 as the
application circuit ground reference. This type of circuit is applicable to those PDs that don’t have outside
connections other than the Ethernet cable, and where the load requirements can be met with lower efficiency.
This form of buck converter places the switch in the low side instead of the high side, with the output referenced
to the positive rail. It allows a low-side control section to drive a step-down topology. The load operates properly
from the differential output voltage because PoE is a floating power delivery method. There is no absolute ground
reference. This is situation analogous to an ungrounded adapter output. The level translator allows use of this
topology without the penalty of external components for accurately sensing an output voltage that doesn’t have
the same ground reference.
The error amplifier and level translator are configured by tying MODE low and SEN to the high-side referenced
output. Tying BL low selects the short blanking because the reverse recovery of the free-wheeling diode, D4, is
relatively short.
The PoE front end is the same as the isolated flyback example. The input π-filter is formed by C2, L1, C4, and
C5, and provides bulk energy storage and EMI filtering. The buck topology consists of inductor L2, switch Q2,
and diode D4. The output voltage is sensed by R7, R6, and R5, with the fed back voltage across R5. C3 allows
the feedback-signal ac component through the translator, reducing the required ac gain of the compensation.
The TPS23750 level translator, behind pins SENP and SEN, reflects the voltage across R5 to the error amplifier,
which is referenced to RTN. The level translator provides a precision method of sensing the output voltage
without requiring external components, and is automatically engaged when SEN is connected to the high side.
The internal 15 kΩ resistor between the translator output and FB, in conjunction with the feedback between
COMP and FB, completes the control loop error amplifier. The compensation components are C7, R2, and C6. A
maximum 50% duty cycle limit makes output voltages to 15 V possible
REFERENCES
1. Designing Stable Control Loops, Dan Mitchell and Bob Mammano, TI (SLUP173)
2. Current Mode Control of Switching Power Supplies, Lloyd H. Dixon Jr., TI (SLUP075)
3. Design of Flyback Transformers and Filter Inductors, Lloyd H. Dixon Jr., TI (SLUP076)
4. The effects of Leakage Inductance on Multi-Output Flyback Circuits, Lloyd Dixon, TI (SLUP081)
5. Achieving High Efficiency with a Multi-Output CCM Flyback Supply Using Self-Driven Synchronous
Rectifiers, Robert Kollman, TI (SLUP204)
6. PowerPAD™ Thermally Enhanced Package Application Report, TI (SLMA002)
7. Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs, TI (SZZA017A)
8. Digital Designer’s Guide to Linear Voltage Regulators and Thermal Management, Bruce Hunter and Patrick
Rowland, TI (SLVA118)
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