TPS23750
TPS23770
www.ti.com
SLVS590A–JULY 2005–REVISED AUGUST 2005
P
+ 5 V 1.5 Ań0.85 + 8.82 W
IN
44 V * 2 0.75 V ) Ǹ(44 V * 2 0.75 V 2 * 4 8.82 W 20 W
(
)
)
V
+
+ 37.84 V
DD
2
2
8.82 W
37.84 V
ǒ
Ǔ
[
]
[
]
P +
ƪ
1 W
ƫ
) 37.84 V 10 nC 200 kHz ) 37.84 V 2.2 mA + 0.213 W
o
o
o
ǒ
Ǔ
T
+ 65 C ) 0.213 W 45 CńW + 74.6 C
J
Table 4. Temperature Rise Calculator Summary
RLOOP
(Ω)
VDD
(V)
P
(W)
TJ
(°C)
VPSE
44
50.5
57
20
10
0
37.84
47.13
55.5
0.213
0.233
0.258
74.6
75.5
76.6
Three conditions were calculated to determine which resulted in the higher junction temperature. The I2R loss
and bias loss variation with input voltage almost cancelled in this case. The resulting junction temperature is
quite low due in part to the good circuit selections, moderate ambient temperature, and low thermal resistance.
LAYOUT
The layout of the PoE front end must use good practice for power and EMI/ESD. A basic set of
recommendations include:
1. The parts placement must be driven by the power flow in a point-to-point manner such as RJ-45 → Ethernet
transformer → diode bridges → TVS and 0.1 µF capacitor → TPS23750 → bulk capacitor → converter input.
2. There should not be any crossovers of signals from one part of the flow to another.
3. All power leads should be as short as possible with wide power traces and paired signal and return.
4. Spacings consistent with standards such as IEC60950 or IPC2221A should be observed between the 48 V
input voltage rails and between the input and an isolated converter's output.
5. The TPS23750 should be positioned over split local ground planes referenced to VSS for the PoE input, and
to RTN for the converter. While the PoE side may operate without a ground plane, the converter side must
have one. The PowerPAD must be tied to the VSS plane or fill area, especially if power dissipation is a
concern. Logic ground and logic power layers should not be present under the Ethernet input or the
converter primary side.
6. Large copper fills and traces should be used on SMT power dissipating devices, and wide traces or overlay
copper fills should be used in the power path.
7. The converter layout can benefit from basic rules such as:
a. Pair signals to reduce emissions and noise, especially the paths that carry high-current pulses through
the power semiconductors and magnetics.
b. Minimize the length of all the traces that carry high-current pulses.
c. Where possible, use vertical pairing rather than side-side pairing.
d. Keep the high-current and high-voltage switching traces from low-level analog circuits including those
outside the power supply. Pay special attention to FB, COMP, FREQ, and TMR.
e. The current sensing lead to RSP is the most critical, noise-sensitive, signal. It must be protected as in d),
paying attention to exposure to the gate drive signal.
f. Follow adequate spacing around the high voltage sections of the converter.
Two evaluation modules (EVM) which demonstrate these principals have been created for this part.
Documentation, including PCB layouts, are available on-line.
28
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