SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
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IFR[12:1]
INT1
INT2
IER[12:1]
INTM
1
MUX
INT11
INT12
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
(Enable)
(Enable/Flag)
PIEIERx[8:1]
(Flag)
PIEIFRx[8:1]
CPU
0
Global
Enable
INTx
MUX
From
Peripherals
or
External
Interrupts
PIEACKx
Figure 3-8. Multiplexing of Interrupts Using the PIE Block
Table 3-12. PIE Peripheral Interrupts
(1)
CPU
INTERRUPTS
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
INT10
INT11
INT12
PIE INTERRUPTS
INTx.8
WAKEINT
(LPM/WD)
Reserved
Reserved
Reserved
Reserved
SPITXINTD
(SPI-D)
Reserved
Reserved
ECAN1_INTB
(CAN-B)
Reserved
Reserved
Reserved
INTx.7
TINT0
(TIMER 0)
Reserved
Reserved
Reserved
Reserved
SPIRXINTD
(SPI-D)
Reserved
Reserved
ECAN0_INTB
(CAN-B)
Reserved
Reserved
Reserved
INTx.6
ADCINT
(ADC)
INTx.5
XINT2
INTx.4
XINT1
INTx.3
Reserved
INTx.2
SEQ2INT
(ADC)
INTx.1
SEQ1INT
(ADC)
EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT
(ePWM6)
(ePWM5)
(ePWM4)
(ePWM3)
(ePWM2)
(ePWM1)
EPWM6_INT
(ePWM6)
Reserved
Reserved
SPITXINTC
(SPI-C)
Reserved
Reserved
ECAN1_INTA
(CAN-A)
Reserved
Reserved
Reserved
EPWM5_INT
(ePWM5)
Reserved
Reserved
SPIRXINTC
(SPI-C)
Reserved
Reserved
ECAN0_INTA
(CAN-A)
Reserved
Reserved
Reserved
EPWM4_INT
(ePWM4)
ECAP4_INT
(eCAP4)
Reserved
SPITXINTB
(SPI-B)
Reserved
Reserved
SCITXINTB
(SCI-B)
Reserved
Reserved
Reserved
EPWM3_INT
(ePWM3)
ECAP3_INT
(eCAP3)
Reserved
SPIRXINTB
(SPI-B)
Reserved
Reserved
SCIRXINTB
(SCI-B)
Reserved
Reserved
Reserved
EPWM2_INT
(ePWM2)
ECAP2_INT
(eCAP2)
EQEP2_INT
(eQEP2)
SPITXINTA
(SPI-A)
Reserved
I2CINT2A
(I2C-A)
SCITXINTA
(SCI-A)
Reserved
Reserved
Reserved
EPWM1_INT
(ePWM1)
ECAP1_INT
(eCAP1)
EQEP1_INT
(eQEP1)
SPIRXINTA
(SPI-A)
Reserved
I2CINT1A
(I2C-A)
SCIRXINTA
(SCI-A)
Reserved
Reserved
Reserved
(1)
Out of the 96 possible interrupts, 43 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 12).
44
Functional Overview
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