TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com
SPRS439I–JUNE 2007–REVISED MARCH 2011
6.15.1 ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
t
d(BGR)
PWDNADC
t
d(PWD)
Request for
ADC
Conversion
Figure 6-31. ADC Power-Up Control Bit Timing
Table 6-51. ADC Power-Up Delays
PARAMETER(1)
MIN
TYP
MAX
UNIT
td(BGR)
td(PWD)
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3
register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.
5
ms
Delay time for power-down control to be stable. Bit delay time for band-gap
reference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0)
must be set to 1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3
register (PWDNADC)must be set to 1 before any ADC conversions are initiated.
20
50
μs
1
ms
(1) Timings maintain compatibility to the 281x ADC module. The 2833x/2823x ADC also supports driving all 3 bits at the same time and
waiting td(BGR) ms before first conversion.
Table 6-52. Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)(1) (2)
ADC OPERATING MODE
CONDITIONS
BG and REF enabled
VDDA18
VDDA3.3
UNIT
Mode A (Operational Mode):
30
2
mA
•
•
PWD disabled
Mode B:
Mode C:
Mode D:
9
5
5
0.5
20
15
mA
μA
μA
•
•
•
ADC clock enabled
BG and REF enabled
PWD enabled
•
•
•
ADC clock enabled
BG and REF disabled
PWD enabled
•
•
•
ADC clock disabled
BG and REF disabled
PWD enabled
(1) Test Conditions:
SYSCLKOUT = 150 MHz
ADC module clock = 25 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
(2) VDDA18 includes current into VDD1A18 and VDD2A18. VDDA3.3 includes current into VDDA2 and VDDAIO
.
Copyright © 2007–2011, Texas Instruments Incorporated
Electrical Specifications
169
Submit Documentation Feedback
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234
TMS320F28232
TI [ TEXAS INSTRUMENTS ]
