欢迎访问ic37.com |
会员登录 免费注册
发布采购

TMS320F28335ZHHA 参数 Datasheet PDF下载

TMS320F28335ZHHA图片预览
型号: TMS320F28335ZHHA
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号控制器(DSC ) [Digital Signal Controllers (DSCs)]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置PC时钟
文件页数/大小: 195 页 / 2496 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号TMS320F28335ZHHA的Datasheet PDF文件第168页浏览型号TMS320F28335ZHHA的Datasheet PDF文件第169页浏览型号TMS320F28335ZHHA的Datasheet PDF文件第170页浏览型号TMS320F28335ZHHA的Datasheet PDF文件第171页浏览型号TMS320F28335ZHHA的Datasheet PDF文件第173页浏览型号TMS320F28335ZHHA的Datasheet PDF文件第174页浏览型号TMS320F28335ZHHA的Datasheet PDF文件第175页浏览型号TMS320F28335ZHHA的Datasheet PDF文件第176页  
TMS320F28335, TMS320F28334, TMS320F28332  
TMS320F28235, TMS320F28234, TMS320F28232  
SPRS439IJUNE 2007REVISED MARCH 2011  
www.ti.com  
6.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)  
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels  
(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, or  
from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected  
channels on every Sample/Hold pulse. The conversion time and latency of the result register update are  
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register  
update. The selected channels will be sampled simultaneously at the falling edge of the Sample/Hold  
pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC  
clocks wide (maximum).  
NOTE  
In simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,  
and not in other combinations (such as A1/B3, etc.).  
Sample n  
Sample n+2  
Sample n+1  
Analog Input on  
Channel Ax  
Analog Input on  
Channel Bx  
ADC Clock  
Sample and Hold  
SH Pulse  
SMODE Bit  
t
d(SH)  
t
dschA0_n+1  
t
SH  
ADC Event Trigger from  
ePWM or Other Sources  
t
t
dschA0_n  
dschB0_n+1  
t
dschB0_n  
Figure 6-34. Simultaneous Sampling Mode Timing  
Table 6-54. Simultaneous Sampling Mode Timing  
AT 25-MHz  
ADC CLOCK,  
tc(ADCCLK) = 40 ns  
SAMPLE n  
SAMPLE n + 1  
REMARKS  
td(SH)  
Delay time from event trigger to  
2.5tc(ADCCLK)  
sampling  
tSH  
Sample/Hold width/Acquisition  
Width  
(1 + Acqps) *  
tc(ADCCLK)  
40 ns with Acqps = 0 Acqps value = 0-15  
ADCTRL1[8:11]  
td(schA0_n)  
td(schB0_n )  
Delay time for first result to  
appear in Result register  
4tc(ADCCLK)  
160 ns  
200 ns  
120 ns  
120 ns  
Delay time for first result to  
appear in Result register  
5tc(ADCCLK)  
td(schA0_n+1) Delay time for successive results  
to appear in Result register  
(3 + Acqps) * tc(ADCCLK)  
(3 + Acqps) * tc(ADCCLK)  
td(schB0_n+1 ) Delay time for successive results  
to appear in Result register  
172  
Electrical Specifications  
Copyright © 2007–2011, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234  
TMS320F28232  
 复制成功!