TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439I–JUNE 2007–REVISED MARCH 2011
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(1) (2)
Table 6-48. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
MIN
MAX
UNIT
ns
td(HL-HiZ)
td(HL-HAL)
td(HH-HAH)
td(HH-BV)
td(HL-HAL)
Delay time, XHOLD low to Hi-Z on all address, data, and control
Delay time, XHOLD low to XHOLDA low
4tc(XTIM) + 30
5tc(XTIM) + 30
ns
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to bus valid
3tc(XTIM) + 30
ns
4tc(XTIM) + 30
ns
Delay time, XHOLD low to XHOLDA low
4tc(XTIM) + 2tc(XCO) + 30
ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
XCLKOUT
(/1 Mode)
t
d(HL-Hiz)
XHOLD
t
d(HH-HAH)
XHOLDA
t
d(HL-HAL)
t
d(HH-BV)
XR/W
High-Impedance
XZCS0, XZCS6, XZCS7
Valid
XA[19:0]
Valid
High-Impedance
XD[31:0], XD[15:0]
Valid
(A)
(B)
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6-29. External Interface Hold Waveform
166
Electrical Specifications
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