TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439I–JUNE 2007–REVISED MARCH 2011
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12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISIMO
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
(A)
SPISTE
C. In the slave mode, the SPISTE signal should be asserted low at least 0.5 tc(SPC) (minimum) before the valid SPI clock
edge and remain low for at least 0.5 tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-20. SPI Slave Mode External Timing (Clock Phase = 0)
148
Electrical Specifications
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