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TMS320F28335ZHHA 参数 Datasheet PDF下载

TMS320F28335ZHHA图片预览
型号: TMS320F28335ZHHA
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号控制器(DSC ) [Digital Signal Controllers (DSCs)]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置PC时钟
文件页数/大小: 195 页 / 2496 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F28335, TMS320F28334, TMS320F28332  
TMS320F28235, TMS320F28234, TMS320F28232  
www.ti.com  
SPRS439IJUNE 2007REVISED MARCH 2011  
Table 6-33. SPI Master Mode External Timing (Clock Phase = 1)(1) (2) (3) (4) (5)  
SPI WHEN (SPIBRR + 1) IS EVEN OR  
SPIBRR = 0 OR 2  
SPI WHEN (SPIBRR + 1) IS ODD  
AND SPIBRR > 3  
NO.  
UNIT  
MIN  
4tc(LCO)  
MAX  
128tc(LCO)  
0.5tc(SPC)M  
MIN  
MAX  
1
2
tc(SPC)M  
Cycle time, SPICLK  
5tc(LCO)  
127tc(LCO)  
ns  
ns  
tw(SPCH)M  
Pulse duration, SPICLK high  
(clock polarity = 0)  
0.5tc(SPC)M – 10  
0.5tc(SPC)M – 0.5tc(LCO) – 10  
0.5tc(SPC)M – 0.5tc(LCO) – 10  
0.5tc(SPC)M + 0.5tc(LCO) – 10  
0.5tc(SPC)M + 0.5tc(LCO) – 10  
0.5tc(SPC)M – 10  
0.5tc(SPC)M – 0.5tc(LCO)  
0.5tc(SPC)M – 0.5tc(LCO)  
0.5tc(SPC)M + 0.5tc(LCO)  
0.5tc(SPC)M + 0.5tc(LCO)  
tw(SPCL))M  
Pulse duration, SPICLK low  
(clock polarity = 1)  
0.5tc(SPC)M – 10  
0.5tc(SPC)M – 10  
0.5tc(SPC)M – 10  
0.5tc(SPC)M – 10  
0.5tc(SPC)M – 10  
0.5tc(SPC)M – 10  
0.5tc(SPC)M – 10  
35  
0.5tc(SPC)M  
0.5tc(SPC)M  
0.5tc(SPC)M  
3
6
tw(SPCL)M  
Pulse duration, SPICLK low  
(clock polarity = 0)  
ns  
ns  
ns  
ns  
ns  
tw(SPCH)M  
Pulse duration, SPICLK high  
(clock polarity = 1)  
tsu(SIMO-SPCH)M  
tsu(SIMO-SPCL)M  
tv(SPCH-SIMO)M  
tv(SPCL-SIMO)M  
tsu(SOMI-SPCH)M  
tsu(SOMI-SPCL)M  
tv(SPCH-SOMI)M  
tv(SPCL-SOMI)M  
Setup time, SPISIMO data valid before  
SPICLK high (clock polarity = 0)  
Setup time, SPISIMO data valid before  
SPICLK low (clock polarity = 1)  
0.5tc(SPC)M – 10  
7
Valid time, SPISIMO data valid after  
SPICLK high (clock polarity = 0)  
0.5tc(SPC)M – 10  
Valid time, SPISIMO data valid after  
SPICLK low (clock polarity = 1)  
0.5tc(SPC)M – 10  
10  
11  
Setup time, SPISOMI before SPICLK high  
(clock polarity = 0)  
35  
Setup time, SPISOMI before SPICLK low  
(clock polarity = 1)  
35  
35  
Valid time, SPISOMI data valid after  
SPICLK high (clock polarity = 0)  
0.25tc(SPC)M – 10  
0.25tc(SPC)M – 10  
0.5tc(SPC)M – 10  
Valid time, SPISOMI data valid after  
SPICLK low (clock polarity = 1)  
0.5tc(SPC)M – 10  
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.  
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)  
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:  
Master mode transmit 25-MHz MAX, master mode receive 12.5 MHz MAX  
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5 MHz MAX.  
(4) tc(LCO) = LSPCLK cycle time  
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).  
Copyright © 2007–2011, Texas Instruments Incorporated  
Electrical Specifications  
145  
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Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234  
TMS320F28232  
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