TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439I–JUNE 2007–REVISED MARCH 2011
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
SPISOMI
Master Out Data Is Valid
10
Data Valid
11
Master In Data Must
Be Valid
(A)
SPISTE
B. In the master mode, SPISTE goes active 0.5 tc(SPC) (minimum) before valid SPI clock edge. On the trailing
end of the word, the SPISTE will go inactive 0.5 tc(SPC) after the receiving edge (SPICLK) of the last data bit,
except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.
Figure 6-19. SPI Master Mode External Timing (Clock Phase = 1)
146
Electrical Specifications
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