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SPRS439I – JUNE 2007 – REVISED MARCH 2011
shows the SCI module block diagram.
SCICTL1.1
Frame Format and Mode
Parity
Even/Odd
Enable
SCICCR.6 SCICCR.5
Transmitter-Data
Buffer Register
TXWAKE
SCICTL1.3
1
WUT
8
TX FIFO _0
TXSHF
Register
8
SCITXD
TXENA
TX EMPTY
SCICTL2.6
TXRDY
SCICTL2.7
TX INT ENA
SCICTL2.0
TXINT
TX Interrupt Logic
TX
FIFO
Interrupts
To CPU
SCI TX Interrupt Select Logic
SCITXD
TX FIFO _1
-----
TX FIFO _15
SCITXBUF.7-0
TX FIFO Registers
SCIFFENA
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
SCILBAUD. 7 - 0
Baud Rate
LSbyte
Register
8
SCIFFTX.14
AutoBaud Detect Logic
SCIRXD
RXSHF Register
RXWAKE
SCIRXST.1
RXENA
SCICTL1.0
SCICTL2.1
Receive-Data
Buffer Register
SCIRXBUF.7-0
8
RX FIFO _15
-----
SCIRXD
LSPCLK
RXRDY
SCIRXST.6
BRKDT
SCIRXST.5
RX
FIFO
Interrupts
RX/BK INT ENA
RX FIFO _1
RX FIFO _0
RX Interrupt Logic
RXINT
To CPU
SCIRXBUF.7-0
RX FIFO Registers
RXFFOVF
SCIRXST.7
RX Error
SCIRXST.4 - 2
FE OE PE
SCIFFRX.15
RX Error
RX ERR INT ENA
SCICTL1.6
SCI RX Interrupt Select Logic
Figure 4-15. Serial Communications Interface (SCI) Module Block Diagram
Copyright © 2007–2011, Texas Instruments Incorporated
Peripherals
95
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