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TMS320F28335ZJZS 参数 Datasheet PDF下载

TMS320F28335ZJZS图片预览
型号: TMS320F28335ZJZS
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号控制器(DSC ) [Digital Signal Controllers (DSCs)]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置PC时钟
文件页数/大小: 195 页 / 2496 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F28335, TMS320F28334, TMS320F28332  
TMS320F28235, TMS320F28234, TMS320F28232  
SPRS439IJUNE 2007REVISED MARCH 2011  
www.ti.com  
4.11 Serial Peripheral Interface (SPI) Module (SPI-A )  
The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is  
available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of  
programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable  
bit-transfer rate. Normally, the SPI is used for communications between the DSC controller and external  
peripherals or another processor. Typical applications include external I/O or peripheral expansion through  
devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by  
the master/slave operation of the SPI.  
The SPI module features include:  
Four external pins:  
SPISOMI: SPI slave-output/master-input pin  
SPISIMO: SPI slave-input/master-output pin  
SPISTE: SPI slave transmit-enable pin  
SPICLK: SPI serial-clock pin  
NOTE: All four pins can be used as GPIO if the SPI module is not used.  
Two operational modes: master and slave  
Baud rate: 125 different programmable rates.  
LSPCLK  
Baud rate =  
when SPIBRR = 3 to127  
when SPIBRR = 0,1, 2  
(SPIBRR + 1)  
LSPCLK  
Baud rate =  
4
NOTE  
See Section 6 for maximum I/O pin toggling speed.  
Data word length: one to sixteen data bits  
Four clocking schemes (controlled by clock polarity and clock phase bits) include:  
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the  
SPICLK signal and receives data on the rising edge of the SPICLK signal.  
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the  
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.  
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the  
SPICLK signal and receives data on the falling edge of the SPICLK signal.  
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the  
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.  
Simultaneous receive and transmit operation (transmit function can be disabled in software)  
Transmitter and receiver operations are accomplished through either interrupt-driven or polled  
algorithms.  
Nine SPI module control registers: Located in control register frame beginning at address 7040h.  
NOTE  
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.  
When a register is accessed, the register data is in the lower byte (7–0), and the upper byte  
(15–8) is read as zeros. Writing to the upper byte has no effect.  
96  
Peripherals  
Copyright © 2007–2011, Texas Instruments Incorporated  
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Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234  
TMS320F28232