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TMS320F28335ZJZS 参数 Datasheet PDF下载

TMS320F28335ZJZS图片预览
型号: TMS320F28335ZJZS
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号控制器(DSC ) [Digital Signal Controllers (DSCs)]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置PC时钟
文件页数/大小: 195 页 / 2496 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F28335, TMS320F28334, TMS320F28332  
TMS320F28235, TMS320F28234, TMS320F28232  
SPRS439IJUNE 2007REVISED MARCH 2011  
www.ti.com  
4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)  
The devices include three serial communications interface (SCI) modules. The SCI modules support  
digital communications between the CPU and other asynchronous peripherals that use the standard  
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its  
own separate enable and interrupt bits. Both can be operated independently or simultaneously in the  
full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity,  
overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit  
baud-select register.  
Features of each SCI module include:  
Two external pins:  
SCITXD: SCI transmit-output pin  
SCIRXD: SCI receive-input pin  
NOTE: Both pins can be used as GPIO if not used for SCI.  
Baud rate programmable to 64K different rates:  
LSPCLK  
Baud rate =  
Baud rate =  
when BRR ¹ 0  
when BRR = 0  
(BRR + 1) * 8  
LSPCLK  
16  
NOTE  
See Section 6 for maximum I/O pin toggling speed.  
Data-word format  
One start bit  
Data-word length programmable from one to eight bits  
Optional even/odd/no parity bit  
One or two stop bits  
Four error-detection flags: parity, overrun, framing, and break detection  
Two wake-up multiprocessor modes: idle-line and address bit  
Half- or full-duplex operation  
Double-buffered receive and transmit functions  
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms  
with status flags.  
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX  
EMPTY flag (transmitter-shift register is empty)  
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag  
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)  
Separate enable bits for transmitter and receiver interrupts (except BRKDT)  
NRZ (non-return-to-zero) format  
NOTE  
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.  
When a register is accessed, the register data is in the lower byte (7-0), and the upper byte  
(15-8) is read as zeros. Writing to the upper byte has no effect.  
92  
Peripherals  
Copyright © 2007–2011, Texas Instruments Incorporated  
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Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234  
TMS320F28232