TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
www.ti.com
SPRS358F–APRIL 2007–REVISED AUGUST 2008
McBSP1
Transmit
McBSP0
CLKX1
FSX1
DX1
CLKX0
FSX0
DX0
Transmit
CLKR1
FSR1
DR1
CLKR0
FSR0
DR0
Receive
Clock
Receive
Clock
CLKS1
CLKS0
Multichannel Buffered Serial Ports
(McBSPs)
FSYNCCLKN
FSYNCCLKP
FRAMEBURSTN
FRAMEBURSTP
ALTFSYNCPULSE
TRT
ALTFSYNCCLK
TRTCLK
FSYNC
Clock
SMFRAMECLK
Frame Synchroniztion (FSYNC)
AIFTXN[5:0]
AIFTXP[5:0]
Transmit
SCL
SDA
I2C
AIFRXN[5:0]
AIFRXP[5:0]
Receive
Antenna Interface (AIF)
Figure 2-9. McBSP/FSYNC/AIF/I2C Peripheral Signals
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