TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
www.ti.com
SPRS358F–APRIL 2007–REVISED AUGUST 2008
32
Data
DDRD[31:0]
DDRCLKOUTP
DDRCLKOUTN
DDRCAS
DDRRAS
DDRWE
DDRCE
Memory Map
Address
External
DDRDQSP[3:0]
Memory
DDRDQSN[3:0]
Controller
14
DDRA[13:0]
DDRRCVENIN[2:0]
DDRRCVENOUT[2:0]
DDRODT
DDRDQM0
DDRDQM1
DDRDQM2
DDRDQM3
DDRSLRATE
VREFSSTL
Byte Enables
DDRBA0
Bank Address
DDRBA1
DDRBA2
DDR Memory Controller (32-bit Data Bus)
Figure 2-7. DDR Memory Controller Peripheral Signals
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Device Overview
23