TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F–APRIL 2007–REVISED AUGUST 2008
www.ti.com
2.6 Signal Groups Description
AVDD118
SYSCLKP
SYSCLKN
Clock/PLL1
SYSCLKOUT
and
PLL Controller
CORECLKSEL
ALTCORECLKP
ALTCORECLKN
RESETSTAT
RESET
NMI0
Reset and
Interrupts
NMI1
NMI2
XWRST
AVDD218
Clock/PLL2
TMS
TDO
TDI
RSV
TCK
TRST
Reserved
EMU00
EMU01
EMU02
IEEE Standard
1149.1
(JTAG)
Emulation
·
·
·
EMU14
EMU15
EMU16
EMU17
EMU18
Control/Status
Figure 2-6. CPU and Peripheral Signals
22
Device Overview
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