欢迎访问ic37.com |
会员登录 免费注册
发布采购

TMS320TCI6487 参数 Datasheet PDF下载

TMS320TCI6487图片预览
型号: TMS320TCI6487
PDF下载: 下载PDF文件 查看货源
内容描述: 通信基础设施数字信号处理器 [Communications Infrastructure Digital Signal Processor]
分类和应用: 数字信号处理器通信
文件页数/大小: 206 页 / 2183 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号TMS320TCI6487的Datasheet PDF文件第152页浏览型号TMS320TCI6487的Datasheet PDF文件第153页浏览型号TMS320TCI6487的Datasheet PDF文件第154页浏览型号TMS320TCI6487的Datasheet PDF文件第155页浏览型号TMS320TCI6487的Datasheet PDF文件第157页浏览型号TMS320TCI6487的Datasheet PDF文件第158页浏览型号TMS320TCI6487的Datasheet PDF文件第159页浏览型号TMS320TCI6487的Datasheet PDF文件第160页  
TMS320TCI6487  
TMS320TCI6488  
Communications Infrastructure Digital Signal Processor  
SPRS358FAPRIL 2007REVISED AUGUST 2008  
www.ti.com  
8.14.1.2 Timer Watchdog Select  
As mentioned previously, the timers can operate in watchdog mode. When in watchdog mode, the event  
output from the timer can optionally reset the CPU. When used in this type of mode, Timer3, Timer4, and  
Timer 5 correspond to C64x+ Megamodule Core 0, C64x+ Megamodule Core 1, and C64x+ Megamodule  
Core 2, respectively. In order for the event not to trigger the reset when this operation is not desired, the  
Timer watchdog reset selection register (WDRSTSEL) is created to turn this feature on/off. The  
WDRSTSEL register is shown in Figure 8-37 and described in Table 8-56.  
31  
8
Reserved  
R-0 0000 0000 0000 0000 0000 0000 0000  
7
3
2
1
0
Reserved  
WDRSTSEL5  
R/W-0  
WDRSTSEL4  
R/W-0  
WDRSTSEL3  
R/W-0  
R-0 0000 0000 0000 0000 0000 0000 0000  
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset  
Figure 8-37. Timer Watchdog Reset Selection Register (WDRSTSEL)  
Table 8-56. Timer Watchdog Reset Selection Register (WDRSTSEL) Field Descriptions  
Bit  
31:3  
2:2  
Field  
Value Description  
Reserved  
Reserved  
WRDSTSELn  
Reset Select for Watchdog Timer  
0
1
TOUTnL does not cause WDRSTSEL to assert to the corresponding C64x+ megamodule  
TOUTnL causes a reset of the corresponding C64x+ megamodule via the host reset port of the  
LPSC  
8.14.2 Timers Peripheral Description(s)  
Table 8-57. Timer 0 Registers  
HEX ADDRESS  
0291 0000  
ACRONYM  
PID  
REGISTER NAME  
Peripheral ID Register  
0291 0004  
EMUMGT_CLKSPD  
Timer 0 Emulation Management/Clock Speed Register  
Reserved  
0291 0008  
-
-
0291 000C  
Reserved  
0291 0010  
TIMLO  
TIMHI  
PRDLO  
PRDHI  
TCR  
TGCR  
WDTCR  
-
Timer 0 Counter Register Low  
Timer 0 Counter Register High  
Timer 0 Period Register Low  
Timer 0 Period Register High  
Timer 0 Control Register  
Timer 0 Global Control Register  
Timer 0 Watchdog Timer Control Register  
Reserved  
0291 0014  
0291 0018  
0291 001C  
0291 0020  
0291 0024  
0291 0028  
0291 002C  
0291 0030  
-
Reserved  
0291 0034 - 0291 FFFF  
-
Reserved  
156  
Peripheral Information and Electrical Specifications  
Submit Documentation Feedback  
 
 
 复制成功!