TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
Table 5-21. McBSP Transmit and Receive Switching Characteristics(1)
5416-120
5416-160
PARAMETER
UNIT
MIN
MAX
tc(BCKRX)
tw(BCKRXH)
tw(BCKRXL)
Cycle time, BCLKR/X(2)
Pulse duration, BCLKR/X high(2)
Pulse duration, BCLKR/X low(2)
BCLKR/X int
BCLKR/X int
BCLKR/X int
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BFSX int
4P(3)
D – 1(4) D + 1(4)
C – 1(4) C + 1(4)
ns
ns
ns
ns
ns
– 3
0
3
6
td(BCKRH-BFRV)
td(BCKXH-BFXV)
tdis(BCKXH-BDXHZ)
Delay time, BCLKR high to internal BFSR valid
Delay time, BCLKX high to internal BFSX valid
– 1
3
5
ns
ns
11
6
Disable time, BCLKX high to BDX high impedance following last data
bit of transfer
10
10
20
20
30
7
– 1(5)
3
– 1(5)
DXENA = 0
Delay time, BCLKX high to BDX valid
DXENA = 1
td(BCKXH-BDXV)
ns
ns
3
–1(5)
3
Delay time, BFSX high to BDX valid
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
td(BFXH-BDXV)
BFSX ext
11
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If the polaritiy of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Note that in some cases, for example when driving another 54x device McBSP, maximum serial port clocking rates may not be
achievable at maximum CPU clock frequency due to transmitted data timings and corresponding receive timing requirements. A
separate detailed timing analysis should be performend for each specific McBSP interface.
(3) P = 0.5 * processor clock.
(4) T = BCLKRX period = (1 + CLKGDV) * 2P
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 +1) * 2P when CLKGDV is even
(5) Minimum delay times also represent minimum output hold times.
t
c(BCKRX)
t
w(BCKRXH)
w(BCKRXL)
t
t
r(BCKRX)
f(BCKRX)
t
BCLKR
BFSR (int)
BFSR (ext)
BDR
t
d(BCKRH-BFRV)
t
d(BCKRH-BFRV)
t
su(BFRH-BCKRL)
t
h(BCKRL-BFRH)
t
su(BDRV-BCKRL)
t
h(BCKRL-BDRV)
(n-2)
(n-3)
Bit(n-1)
Figure 5-21. McBSP Receive Timings
Electrical Specifications
79
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