TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
5.5.2 Memory Write
Table 5-9 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5tc(CO) (see
Figure 5-7).
Table 5-9. Memory Write Switching Characteristics
5416-120
5416-160
PARAMETER
UNIT
MIN
–1
MAX
td(CLKL-A)
tsu(A)MSL
Delay time, CLKOUT low to address valid(1)
Setup time, address valid before MSTRB low(1)
Delay time, CLKOUT low to data valid
Setup time, data valid before MSTRB high
Hold time, data valid after MSTRB high
Delay time, CLKOUT low to MSTRB low
Pulse duration, MSTRB low
4
ns
ns
ns
ns
ns
ns
ns
ns
2H – 3
–1
td(CLKL-D)W
tsu(D)MSH
th(D)MSH
4
2H – 4 2H + 6
2H – 5 2H + 6
td(CLKL-MSL)
tw(SL)MS
–1
2H – 2
0
4
td(CLKL-MSH)
Delay time, CLKOUT low to MSTRB high
4
(1) Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
CLKOUT
t
d(CLKL-A)
t
d(CLKL-A)
t
d(CLKL-D)W
t
su(A)MSL
A[22:0]
(see Note A)
t
su(D)MSH
t
h(D)MSH
D[15:0]
t
d(CLKL-MSL)
t
d(CLKL-MSH)
t
w(SL)MS
MSTRB
R/W
(see Note A)
PS/DS
(see Note A)
A. Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-7. Memory Write (MSTRB = 0)
Electrical Specifications
63
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