TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
CLKOUT
t
t
d(CLKL-A)
d(CLKL-A)
t
d(CLKL-IOSL)
t
d(CLKL-IOSH)
A[22:0]
(see Note A)
t
a(A)M1
t
su(D)R
t
h(D)R
D[15:0]
IOSTRB
R/W
(see Note A)
IS
(see Note A)
A. Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-8. Parallel I/O Port Read (IOSTRB = 0)
5.5.4 I/O Write
Table 5-12 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5tc(CO) (see
Figure 5-9).
Table 5-12. I/O Write Switching Characteristics
5416-120
5416-160
PARAMETER
UNIT
MIN
– 1
MAX
td(CLKL-A)
tsu(A)IOSL
Delay time, CLKOUT low to address valid(1)
Setup time, address valid before IOSTRB low(1)
Delay time, CLKOUT low to write data valid
Setup time, data valid before IOSTRB high
Hold time, data valid after IOSTRB high
Delay time, CLKOUT low to IOSTRB low
Pulse duration, IOSTRB low
4
ns
ns
ns
ns
ns
ns
ns
ns
2H – 3
– 1
td(CLKL-D)W
tsu(D)IOSH
th(D)IOSH
4
2H – 4 2H + 6
2H – 5 2H + 6
td(CLKL-IOSL)
tw(SL)IOS
– 1
2H – 2
0
4
td(CLKL-IOSH)
Delay time, CLKOUT low to IOSTRB high
4
(1) Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Electrical Specifications
65
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