TMS320VC5416
Fixed-Point Digital Signal Processor
www.ti.com
SPRS095O–MARCH 1999–REVISED JANUARY 2005
5.4.2 Multiply-By-N Clock Option (PLL Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate
the internal machine cycle. The selection of the clock mode and the value of N is described in Section
Section 3.10. Following reset, the software PLL can be programmed for the desired multiplication factor. Refer to
the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131) for detailed
information on programming the PLL.
When an external clock source is used, the external frequency injected must conform to specifications listed in
Table 5-5.
Table 5-5 and Table 5-6 assume testing over recommended operating conditions and H = 0.5tc(CO) (see
Figure 5-4).
Table 5-5. Multiply-By-N Clock Option Timing Requirements
5416-120
5416-160
Unit
MIN
20
MAX
Integer PLL multiplier N (N = 1-15)(1)
PLL multiplier N = x.5(1)
PLL multiplier N = x.25, x.75(1)
200
100
50
4
tc(CI)
Cycle time, X2/CLKIN
20
ns
20
tf(CI)
Fall time, X2/CLKIN
ns
ns
ns
ns
tr(CI)
Rise time, X2/CLKIN
4
tw(CIL)
tw(CIH)
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
4
4
(1) N is the multiplication factor.
Table 5-6. Multiply-By-N Clock Option Switching Characteristics
5416-120
TYP
5416-160
TYP
PARAMETER
Cycle time, CLKOUT
Unit
MIN
8.33
4
MAX
MIN
6.25
4
MAX
tc(CO)
td(CI-CO)
tf(CO)
ns
ns
ns
ns
ns
ns
ms
Delay time, X2/CLKIN high/low to CLKOUT high/low
Fall time, CLKOUT
7
2
11
7
2
11
tr(CO)
tw(COL)
tw(COH)
tp
Rise time, CLKOUT
2
2
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
Transitory phase, PLL lock-up time
H – 2
H – 2
H
H
H + 1 H – 2
H + 1 H – 2
30
H
H
H + 1
H + 1
30
t
t
f(CI)
w(CIH)
t
r(CI)
t
t
c(CI)
w(CIL)
X2/CLKIN
t
d(CI-CO)
t
t
f(CO)
t
w(COH)
t
c(CO)
w(COL)
t
r(CO)
t
p
CLKOUT
(see Note A)
Unstable
A. The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as
00 (CLKOUT not divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5-4. Multiply-By-One Clock Timing
Electrical Specifications
59
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