T M S3 2 0 VC5 402
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
interrupts (continued)
The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in Figure 8.
15–14
RES
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMAC5
DMAC4
BXINT1 BRINT1 HPINT
or or
DMAC3 DMAC2
INT3
TINT1
or
DMAC1 DMAC0
RES
or
BXINT0 BRINT0
TINT0
INT2
INT1
INT0
Figure 8. IFR and IMR Registers
Table 14. IFR and IMR Register Bit Fields
BIT
FUNCTION
NUMBER
NAME
15–14
13
–
Reserved for future expansion
DMAC5
DMAC4
DMA channel 5 interrupt flag/mask bit
DMA channel 4 interrupt flag/mask bit
12
This bit can be configured as either the McBSP1 transmit interrupt flag/mask bit, or the DMA
channel 3 interrupt flag/mask bit. The selection is made in the DMPREC register.
11
10
BXINT1/DMAC3
BRINT1/DMAC2
This bit can be configured as either the McBSP1 receive interrupt flag/mask bit, or the DMA
channel 2 interrupt flag/mask bit. The selection is made in the DMPREC register.
9
8
HPINT
INT3
Host to ’54x interrupt flag/mask
External interrupt 3 flag/mask
This bit can be configured as either the timer1 interrupt flag/mask bit, or the DMA channel 1
interrupt flag/mask bit. The selection is made in the DMPREC register.
7
6
TINT1/DMAC1
DMAC0
This bit can be configured as either reserved, or the DMA channel 0 interrupt flag/mask bit. The
selection is made in the DMPREC register.
5
4
3
2
1
0
BXINT0
BRINT0
TINT0
INT2
McBSP0 transmit interrupt flag/mask bit
McBSP0 receive interrupt flag/mask bit
Timer 0 interrupt flag/mask bit
External interrupt 2 flag/mask bit
External interrupt 1 flag/mask bit
External interrupt 0 flag/mask bit
INT1
INT0
32
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