T MS 3 20 VC 54 02
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 13.
Table 13. Interrupt Locations and Priorities
LOCATION
PRIORITY
NAME
FUNCTION
DECIMAL
0
HEX
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
50
54
RS, SINTR
NMI, SINT16
SINT17
1
2
Reset (hardware and software reset)
Nonmaskable interrupt
Software interrupt #17
Software interrupt #18
Software interrupt #19
Software interrupt #20
Software interrupt #21
Software interrupt #22
Software interrupt #23
Software interrupt #24
Software interrupt #25
Software interrupt #26
Software interrupt #27
Software interrupt #28
Software interrupt #29
Software interrupt #30
External user interrupt #0
External user interrupt #1
External user interrupt #2
Timer0 interrupt
4
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
SINT18
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
SINT19
SINT20
SINT21
SINT22
SINT23
SINT24
SINT25
SINT26
SINT27
SINT28
SINT29
SINT30
INT0, SINT0
INT1, SINT1
INT2, SINT2
TINT0, SINT3
4
5
6
BRINT0, SINT4
BXINT0, SINT5
7
McBSP #0 receive interrupt
McBSP #0 transmit interrupt
8
Reserved (default) or DMA channel 0 inter-
rupt. The selection is made in the DMPREC
register.
Reserved(DMAC0), SINT6
TINT1(DMAC1), SINT7
88
92
58
9
Timer1 interrupt (default) or DMA channel 1
interrupt. The selection is made in the
DMPREC register.
5C
10
INT3, SINT8
96
60
64
11
12
External user interrupt #3
HPI interrupt
HPINT, SINT9
100
McBSP #1 receive interrupt (default) or DMA
channel 2 interrupt. The selection is made in
the DMPREC register.
BRINT1(DMAC2), SINT10
BXINT1(DMAC3), SINT11
104
108
68
13
14
McBSP #1 transmit interrupt (default) or DMA
channel 3 interrupt. The selection is made in
the DMPREC register.
6C
DMAC4,SINT12
DMAC5,SINT13
Reserved
112
116
70
74
15
16
—
DMA channel 4 interrupt
DMA channel 5 interrupt
Reserved
120–127
78–7F
31
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