T M S3 2 0 VC5 402
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
DMA subbank addressed registers (continued)
Table 12. DMA Subbank Addressed Registers
DMA
SUB-
ADDRESS
NAME
ADDRESS
DESCRIPTION
DMA channel 0 source address register
DMSRC0
DMDST0
DMCTR0
DMSFC0
DMMCR0
DMSRC1
DMDST1
DMCTR1
DMSFC1
DMMCR1
DMSRC2
DMDST2
DMCTR2
DMSFC2
DMMCR2
DMSRC3
DMDST3
DMCTR3
DMSFC3
DMMCR3
DMSRC4
DMDST4
DMCTR4
DMSFC4
DMMCR4
DMSRC5
DMDST5
DMCTR5
DMSFC5
DMMCR5
DMSRCP
DMDSTP
DMIDX0
DMIDX1
DMFRI0
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
DMA channel 0 destination address register
DMA channel 0 element count register
DMA channel 0 sync select and frame count register
DMA channel 0 transfer mode control register
DMA channel 1 source address register
DMA channel 1 destination address register
DMA channel 1 element count register
DMA channel 1 sync select and frame count register
DMA channel 1 transfer mode control register
DMA channel 2 source address register
DMA channel 2 destination address register
DMA channel 2 element count register
DMA channel 2 sync select and frame count register
DMA channel 2 transfer mode control register
DMA channel 3 source address register
DMA channel 3 destination address register
DMA channel 3 element count register
DMA channel 3 sync select and frame count register
DMA channel 3 transfer mode control register
DMA channel 4 source address register
DMA channel 4 destination address register
DMA channel 4 element count register
DMA channel 4 sync select and frame count register
DMA channel 4 transfer mode control register
DMA channel 5 source address register
DMA channel 5 destination address register
DMA channel 5 element count register
DMA channel 5 sync select and frame count register
DMA channel 5 transfer mode control register
DMA source program page address (common channel)
DMA destination program page address (common channel)
DMA element index address register 0
DMA element index address register 1
DMA frame index register 0
DMFRI1
DMA frame index register 1
DMGSA
DMA global source address reload register
DMA global destination address reload register
DMA global count reload register
DMGDA
DMGCR
DMGFR
DMA global frame count reload register
30
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