T MS 3 20 VC 54 02
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
electrical characteristics over recommended operating case temperature range (unless otherwise
noted)
†
TYP
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
MIN
2.4
MAX
UNIT
V
V
I
I
= MAX
= MAX
V
OH
OH
0.4
V
OL
OL
Bus holders enabled, DV
DD
= MAX,
Input current for
outputs in high
impedance
D[15:0], HD[7:0]
–175
175
V = V
to DV
I
SS
DD
I
IZ
µA
All other inputs
DV
= MAX, V = V
SS
to DV
DD
–5
5
DD
O
}
X2/CLKIN
–40
40
TRST
With internal pulldown
With internal pulldown
–5
–5
300
300
Input current
HPIENA
(V = V
I
SS
I
I
µA
to DV
)
DD
With internal pullups,
HPIENA = 0
w
TMS, TCK, TDI, HPI
–300
–5
5
5
All other input-only pins
¶
#
||
I
I
Supply current, core CPU
Supply current, pins
CV
DV
= 1.8 V, f
= 3.3 V, f
= 100 MHz , T = 25°C
45
mA
DDC
DD
DD
clock
C
¶
= 100 MHz , T = 25°C
30
2
mA
mA
DDP
clock
C
IDLE2
IDLE3
PLL × 1 mode, 100 MHz input
Supply current,
standby
I
DD
Divide-by-two mode, CLKIN stopped
20
µA
C
C
Input capacitance
Output capacitance
5
5
pF
pF
i
o
†
‡
All values are typical unless otherwise specified.
All revisions of the ’5402 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN pin.
It should be noted that the X2/CLKIN pin is referenced to the device 1.8V power supply (CVdd), rather than the 3V I/O supply (DVdd). Refer to
the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.
HPI input signals except for HPIENA.
§
¶
#
Clock mode: PLL × 1 with external source
This value represents the current consumption of the CPU, on-chip memory, and on-chip peripherals. Conditions include: program execution
from on-chip RAM, with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed.
This value was obtained using the following conditions: external memory writes at a rate of 20 million writes per second, CLKOFF=0, full-duplex
operation of McBSP0 and McBSP1 at a rate of 10 million bits per second each, and 15-pF loads on all outputs. For more details on how this
calculation is performed, refer to the Calculation of TMS320C54x Power Dissipation Application Report (literature number SPRA164).
||
PARAMETER MEASUREMENT INFORMATION
I
OL
50 Ω
Output
Under
Test
Tester Pin
Electronics
V
Load
C
T
I
OH
Where:
I
I
= 1.5 mA (all outputs)
= 300 µA (all outputs)
= 1.5 V
OL
OH
V
Load
C
= 40 pF typical load circuit capacitance
T
Figure 9. 3.3-V Test Load Circuit
35
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