T M S3 2 0 VC5 402
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory-mapped registers (continued)
Table 10. Peripheral Memory-Mapped Registers
NAME
DRR20
ADDRESS
20h
DESCRIPTION
McBSP0 data receive register 2
TYPE
McBSP #0
McBSP #0
McBSP #0
McBSP #0
Timer0
DRR10
DXR20
DXR10
TIM
21h
McBSP0 data receive register 1
McBSP0 data transmit register 2
McBSP0 data transmit register 1
Timer0 register
22h
23h
24h
PRD
25h
Timer0 period counter
Timer0 control register
Reserved
Timer0
TCR
26h
Timer0
–
27h
SWWSR
BSCR
–
28h
Software wait-state register
Bank-switching control register
Reserved
External Bus
External Bus
29h
2Ah
SWCR
HPIC
–
2Bh
Software wait-state control register
HPI control register
External Bus
HPI
2Ch
2Dh–2Fh
30h
Reserved
TIM1
PRD1
TCR1
–
Timer1 register
Timer1
Timer1
Timer1
31h
Timer1 period counter
Timer1 control register
Reserved
32h
33h–37h
38h
†
SPSA0
SPSD0
–
McBSP0 subbank address register
McBSP #0
McBSP #0
†
39h
McBSP0 subbank data register
3Ah–3Bh
3Ch
Reserved
GPIOCR
GPIOSR
–
General-purpose I/O pins control register
General-purpose I/O pins status register
Reserved
GPIO
GPIO
3Dh
3Eh–3Fh
40h
DRR21
DRR11
DXR21
DXR11
–
McBSP1 data receive register 2
McBSP1 data receive register 1
McBSP1 data transmit register 2
McBSP1 data transmit register 1
Reserved
McBSP #1
McBSP #1
McBSP #1
McBSP #1
41h
42h
43h
44h–47h
48h
†
SPSA1
SPSD1
–
McBSP1 subbank address register
McBSP #1
McBSP #1
†
49h
McBSP1 subbank data register
4Ah–53h
54h
Reserved
DMPREC
DMSA
DMSDI
DMSDN
CLKMD
–
DMA channel priority and enable control register
DMA
DMA
DMA
DMA
PLL
‡
55h
DMA subbank address register
‡
56h
DMA subbank data register with autoincrement
‡
57h
DMA subbank data register
Clock mode register
Reserved
58h
59h–5Fh
†
‡
See Table 11 for a detailed description of the McBSP control registers and their sub-addresses.
See Table 12 for a detailed description of the DMA subbank addressed registers.
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