T M S3 2 0 VC5 402
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
DMA channel interrupt selection
The DMA controller can generate a CPU interrupt for each of the six channels. However, the interrupt sources
for channels 0,1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 2 and 3 share an interrupt
line with the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11), and DMA channel 1 shares an
interrupt line with timer 1 (IMR/IFR bit 7). The interrupt source for DMA channel 0 is shared with a reserved
interrupt source. When the ’5402 is reset, the interrupts from these four DMA channels are deselected. The
INTSEL bit field in the DMA channel priority and enable control (DMPREC) register can be used to select these
interrupts, as shown in Table 8.
Table 8. DMA Channel Interrupt Selection
INTSEL Value
00b (reset)
01b
IMR/IFR[6]
Reserved
Reserved
DMAC0
IMR/IFR[7]
TINT1
IMR/IFR[10]
BRINT1
IMR/IFR[11]
BXINT1
TINT1
DMAC2
DMAC3
10b
DMAC1
DMAC2
DMAC3
11b
Reserved
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI [ TEXAS INSTRUMENTS ]
