T MS 3 20 VC 54 02
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
memory map
Page 0 Program
Page 0 Program
Data
Hex
0000
Hex
0000
Hex
0000
Memory
Mapped
Registers
Reserved
(OVLY = 1)
External
(OVLY = 0)
Reserved
(OVLY = 1)
External
(OVLY = 0)
005F
0060
Scratch-Pad
RAM
007F
0080
007F
0080
007F
0080
On-Chip DARAM
(OVLY = 1)
On-Chip DARAM
(OVLY = 1)
On-Chip DARAM
(16K x 16-bit)
External
(OVLY = 0)
External
(OVLY = 0)
3FFF
4000
3FFF
4000
3FFF
4000
External
External
EFFF
F000
EFFF
F000
External
ROM (DROM=1)
or External
On-Chip ROM
(4K x 16-bit)
(DROM=0)
FEFF
FF00
FEFF
FF00
Reserved
Reserved
(DROM=1)
or External
(DROM=0)
FF7F
FF80
FF7F
FF80
Interrupts
(External)
Interrupts
(On-Chip)
FFFF
FFFF
FFFF
MP/MC= 1
(Microprocessor Mode)
MP/MC= 0
(Microcomputer Mode)
Figure 1. Memory Map
relocatable interrupt vector table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch
instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate
interrupt service routine with minimal overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However,
these vectors can be remapped to the beginning of any 128-word page in program space after device reset.
This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register (see Figure 2) with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped
to the new 128-word page.
NOTE: The hardware reset (RS) vector cannot be remapped because a hardware reset loads the IPTR
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.
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