ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢈꢈꢊ
ꢋ ꢌꢍ ꢎꢏꢐꢑꢒ ꢌ ꢓꢀ ꢏꢌ ꢔꢌ ꢀꢕꢖ ꢂꢌ ꢔ ꢓꢕꢖ ꢑꢗ ꢒ ꢆꢎ ꢂ ꢂꢒ ꢗ ꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2005
RESET TIMING (CONTINUED)
CLKOUT1
CLKOUT2
1
15
14
RESET
2
4
6
8
3
§
ECLKIN
5
7
†
†
EMIF Z Group
EMIF High Group
9
†
EMIF Low Group
High Group
10
12
11
13
†
†
‡
Z Group
HD[8, 4:3]
§
†
ECLKIN should be provided during reset in order to drive EMIF signals to the correct reset values. ECLKOUT continues to clock as long as
ECLKIN is provided.
EMIF Z group consists of:
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE
EMIF high group consists of: HOLDA
EMIF low group consists of: BUSREQ
High group consists of:
Z group consists of:
HD[8, 4:3] are the endianness and boot configuration pins during device reset.
HRDY and HINT
HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1.
‡
Figure 31. Reset Timing
63
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