ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢄꢈꢈ ꢉ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢊ
ꢋ ꢌ ꢍꢎꢏ ꢐꢑ ꢒꢌ ꢓ ꢀ ꢏ ꢌ ꢔꢌ ꢀꢕꢖ ꢂ ꢌ ꢔꢓ ꢕꢖ ꢑ ꢗꢒ ꢆꢎꢂ ꢂꢒ ꢗꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2005
peripheral register descriptions (continued)
†
Table 7. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE
0200 0000
ACRONYM
QOPT
QSRC
QCNT
QDST
QIDX
REGISTER NAME
QDMA options parameter register
QDMA source address register
QDMA frame count register
QDMA destination address register
QDMA index register
0200 0004
0200 0008
0200 000C
0200 0010
0200 0014 − 0200 001C
0200 0020
−
Reserved
QSOPT
QSSRC
QSCNT
QSDST
QSIDX
QDMA pseudo options register
0200 0024
QDMA pseudo source address register
QDMA pseudo frame count register
QDMA pseudo destination address register
QDMA pseudo index register
0200 0028
0200 002C
0200 0030
†
All the QDMA and Pseudo registers are write-accessible only
Table 8. Interrupt Selector Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Selects which interrupts drive CPU interrupts
10−15 (INT10−INT15)
019C 0000
MUXH
Interrupt multiplexer high
Selects which interrupts drive CPU interrupts 4−9
(INT04−INT09)
019C 0004
MUXL
Interrupt multiplexer low
Sets the polarity of the external interrupts
(EXT_INT4−EXT_INT7)
019C 0008
EXTPOL
−
External interrupt polarity
Reserved
019C 000C − 019F FFFF
14
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