ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢉ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢄꢈꢈꢊ
ꢋ ꢌꢍ ꢎꢏꢐꢑꢒ ꢌ ꢓꢀ ꢏꢌ ꢔꢌ ꢀꢕꢖ ꢂꢌ ꢔ ꢓꢕꢖ ꢑꢗ ꢒ ꢆꢎ ꢂ ꢂꢒ ꢗ ꢂ
SPRS073L − AUGUST 1998 − REVISED JUNE 2005
peripheral register descriptions (continued)
Table 9. McBSP 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and DMA/EDMA
controller can only read this
register; they cannot write to
it.
018C 0000
DRR0
McBSP0 data receive register via Peripheral Bus
0x3000 0000 − 0x33FF FFFF
018C 0004
DRR0
DXR0
DXR0
SPCR0
RCR0
XCR0
SRGR0
MCR0
RCER0
XCER0
PCR0
−
McBSP0 data receive register via EDMA Bus
McBSP0 data transmit register via Peripheral Bus
McBSP0 data transmit register via EDMA Bus
McBSP0 serial port control register
McBSP0 receive control register
0x3000 0000 − 0x33FF FFFF
018C 0008
018C 000C
018C 0010
McBSP0 transmit control register
018C 0014
McBSP0 sample rate generator register
McBSP0 multichannel control register
McBSP0 receive channel enable register
McBSP0 transmit channel enable register
McBSP0 pin control register
018C 0018
018C 001C
018C 0020
018C 0024
018C 0028 − 018F FFFF
Reserved
Table 10. McBSP 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and DMA/EDMA
controller can only read this
register; they cannot write to
it.
0190 0000
DRR1
Data receive register via Peripheral Bus
0x3400 0000 − 0x37FF FFFF
0190 0004
DRR1
DXR1
DXR1
SPCR1
RCR1
XCR1
SRGR1
MCR1
RCER1
XCER1
PCR1
−
McBSP1 data receive register via EDMA Bus
McBSP1 data transmit register via Peripheral Bus
McBSP1 data transmit register via EDMA Bus
McBSP1 serial port control register
McBSP1 receive control register
0x3400 0000 − 0x37FF FFFF
0190 0008
0190 000C
0190 0010
McBSP1 transmit control register
0190 0014
McBSP1 sample rate generator register
McBSP1 multichannel control register
McBSP1 receive channel enable register
McBSP1 transmit channel enable register
McBSP1 pin control register
0190 0018
0190 001C
0190 0020
0190 0024
0190 0028 − 0193 FFFF
Reserved
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TI [ TEXAS INSTRUMENTS ]
