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TMS320VC5407PGE 参数 Datasheet PDF下载

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型号: TMS320VC5407PGE
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [Fixed-Point Digital Signal Processors]
分类和应用: 数字信号处理器
文件页数/大小: 110 页 / 1351 K
品牌: TI [ TEXAS INSTRUMENTS ]
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Electrical Specifications  
Table 534. HPI8 Mode Switching Characteristics  
PARAMETER  
MIN  
MAX  
UNIT  
t
Enable time, HD driven from DS low  
0
10  
ns  
en(DSL-HD)  
Case 1a: Memory accesses when DMAC is active  
18P+10t  
36P+10t  
10  
w(DSH)  
in 16-bit mode and t  
< I8H  
w(DSH)  
Case 1b: Memory accesses when DMAC is active  
w(DSH)  
in 32-bit mode and t  
I8H  
w(DSH)  
Case 1c: Memory accesses when DMAC is active  
in 16-bit mode and t  
I8H  
w(DSH)  
Delay time, DS low to HD valid  
for first byte of an HPI read  
Case 1d: Memory accesses when DMAC is active  
t
ns  
d(DSL-HDV1)  
10  
in 32-bit mode and t  
I8H  
w(DSH)  
Case 2a: Memory accesses when DMAC is inactive  
10P+15t  
10  
w(DSH)  
and t  
< 10H  
w(DSH)  
Case 2b: Memory accesses when DMAC is inactive  
and t  
10H  
w(DSH)  
Case 3: Register accesses  
10  
10  
t
t
t
t
Delay time, DS low to HD valid for second byte of an HPI read  
Hold time, HD valid after DS high, for a HPI read  
Valid time, HD valid after HRDY high  
ns  
ns  
ns  
ns  
d(DSL-HDV2)  
h(DSH-HDV)R  
v(HYH-HDV)  
d(DSH-HYL)  
2
2
8
Delay time, DS high to HRDY low  
Case 1a: Memory accesses when DMAC is active  
in 16-bit mode  
18P+6  
36P+6  
Case 1b: Memory accesses when DMAC is active  
Delay time, DS high to HRDY  
high  
t
ns  
d(DSH-HYH)  
in 32-bit mode  
Case 2: Memory accesses when DMAC is inactive  
10P+6  
§
Case 3: Write accesses to HPIC register  
6P+6  
6
9
6
ns  
ns  
ns  
t
t
t
Delay time, HCS low/high to HRDY low/high  
Delay time, CLKOUT high to HRDY high  
Delay time, CLKOUT high to HINT change  
d(HCS-HRDY)  
d(COH-HYH)  
d(COH-HTX)  
Delay time, CLKOUT high to HDx output change. HDx is configured as  
general-purpose output  
a
t
5
ns  
d(COH-GPIO)  
DMAC stands for direct memory access controller (DMAC). The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times  
are affected by DMAC activity.  
The HRDY output is always high when the HCS input is high, regardless of DS timings.  
This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur asynchronously,  
and do not cause HRDY to be deasserted.  
§
101  
November 2001 Revised April 2004  
SPRS007D