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TMS320VC5407PGE 参数 Datasheet PDF下载

TMS320VC5407PGE图片预览
型号: TMS320VC5407PGE
PDF下载: 下载PDF文件 查看货源
内容描述: 定点数字信号处理器 [Fixed-Point Digital Signal Processors]
分类和应用: 数字信号处理器
文件页数/大小: 110 页 / 1351 K
品牌: TI [ TEXAS INSTRUMENTS ]
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Electrical Specifications  
5.15.2 HPI16 Mode  
Table 535 and Table 536 assume testing over recommended operating conditions and P = 0.5 * processor  
clock (see Figure 532 through Figure 534). In the following tables, DS refers to the logical OR of HCS,  
HDS1, and HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These timings are  
shown assuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP Reference Set,  
Volume 5: Enhanced Peripherals (literature number SPRU302) for additional information.  
Table 535. HPI16 Mode Timing Requirements  
MIN  
6
MAX  
UNIT  
ns  
t
t
Setup time, HR/W valid before DS falling edge  
Hold time, HR/W valid after DS falling edge  
su(HBV-DSL)  
5
ns  
h(DSL-HBV)  
t
t
t
t
t
Setup time, address valid before DS rising edge (write)  
Setup time, address valid before DS falling edge (read)  
Hold time, address valid after DS rising edge  
Pulse duration, DS low  
5
ns  
ns  
ns  
ns  
ns  
su(HAV-DSH)  
su(HAV-DSL)  
h(DSH-HAV)  
w(DSL)  
(4P 6)  
1
30  
Pulse duration, DS high  
10  
w(DSH)  
Reads  
Writes  
Reads  
Writes  
Reads  
Writes  
10P + 30  
10P + 10  
16P + 30  
16P + 10  
24P + 30  
24P + 10  
8
Memory accesses with no DMA activity.  
Cycle time, DS rising edge to  
next DS rising edge  
t
Memory accesses with 16-bit DMA activity.  
Memory accesses with 32-bit DMA activity.  
ns  
c(DSH-DSH)  
t
t
Setup time, HD valid before DS rising edge  
Hold time, HD valid after DS rising edge, write  
ns  
ns  
su(HDV-DSH)W  
2
h(DSH-HDV)W  
104  
SPRS007D  
November 2001 Revised April 2004